Membrane dielectric isolation IC fabrication

• US 5,946,559 A
• Filed: 06/07/1995
• Issued: 08/31/1999
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: ELM TECHNOLOGY CORPORATION
• Inventors: Leedy, Glenn Joseph
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/472,426
• Time in Patent Office: 1,546 Days
• Field of Search: 438/149, 438/151, 438/154, 438/157, 438/156, 438/270, 438/271, 438/283, 438/294, 257/508, 257/506, 257/510, 257/619, 257/622
• US Class Current: 438/157
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/135 : Removal of substrate
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing
• CPC Class Codes: Y10S 438/938 : Lattice strain control or utilization
• CPC Class Codes: Y10S 438/942 : Masking
• CPC Class Codes: Y10S 438/967 : Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 29/4921 : with bonding

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1. A method of forming a field effect transistor having a narrow gate and opposed gate contact, comprising the steps of:

forming a silicon layer less than about 10 μ

m thick;

forming a gate electrode over the principal surface of the silicon layer;

forming a low stress dielectric layer less than about 10 μ

m thick over the silicon layer and over the gate electrode;

forming doped regions in the silicon layer;

etching a groove in the silicon layer from the surface opposing the principal surface thereof in a portion of the silicon layer underlying the gate electrode;

depositing metal in the groove to a predetermined depth;

etching away the opposing surface of the silicon layer to the predetermined depth;

depositing a mask layer on the etched-away surface;

patterning the mask layer, thereby exposing portions of the etched-away surface;

forming additional doped regions in the silicon layer at the exposed portions of the etched-away surface;

removing the mask layer; and

etching away additional portions the etched-away surface to the bottom of the groove, thereby removing all of the deposited metal.

2. The method of claim 1, further comprising the steps of forming a trench in the silicon layer surrounding the active portion of the transistor.

3. A method of forming a transistor, comprising the steps of:

providing a flexible membrane having a thin film of semiconductor material formed on the membrane;

forming a trench in the semiconductor material;

doping portions of the semiconductor material;

laterally growing extensions of the sidewalls of the trench, thereby narrowing the trench to a predetermined width;

filling the remaining width of the trench with semiconductor material doped at a concentration differing from a doping level of the extensions; and

forming an electrical contact to the filled portion of the trench through the flexible membrane.

4. The method of claim 3, further comprising the step of isolating the trench by forming additional trenches in the semiconductor material surrounding the first trench.

5. The method of claim 3, further comprising the steps, prior to the step of laterally growing, of:

forming a mask layer over a principal surface of the thin film of semiconductor material;

etching away sidewalls of the trench, thereby forming a cavity under the mask layer; and

laterally growing a plurality of differently doped layers of semiconductor material on the sidewalls of the cavity.

6. A field effect transistor comprising:

a flexible dielectric membrane having a principal surface;

a semiconductor film formed on the principal surface of the membrane, the semiconductor film including at least three doped layers;

a contact to a first of the three doped layers formed through the membrane;

a contact to a second of the doped layers formed on a principal surface of the semiconductor film;

an insulating layer formed over an edge of the semiconductor film; and

a gate electrode formed overlying the insulating layer.

7. The device of claim 6, wherein a portion of the third layer extends over edges of the first and second layers.

8. The device of claim 6 wherein the third layer is located intermediate of the first and second layers, and a portion of the third layer extends over edges of the first and second layers, and

wherein the contact to the third layer overlies the extended portion of the third layer.

9. A method of forming a field effect transistor comprising the steps of:

providing a membrane comprising a semiconductor layer overlying a low stress dielectric layer;

forming a drain region and a source region laterally spaced apart from the drain region in the semiconductor layer, a portion of the semiconductor layer between the source and drain regions being a gate region;

forming an insulating layer overlying the semiconductor layer; and

forming a gate electrode on the insulating layer, one edge of the gate electrode being in a plane defined by an interface of one of the source region or the drain region and the gate region, and a second edge of the gate electrode extending over the other of the drain region or source region.

10. A method of forming a transistor comprising the steps of:

providing a flexible membrane including a low stress dielectric layer and a semiconductor layer;

forming a first and a second doped regions in the semiconductor layer, the first and second doped regions being vertically spaced apart and separated by a control region;

epitaxially growing an extension of the control region extending over an edge of the semiconductor layer and contacting edges of the first and second doped regions; and

forming electrical contacts to the first and second doped regions and to extension of the control region.