Process of fabricating metal gate electrode

• US 5,946,598 A
• Filed: 12/26/1996
• Issued: 08/31/1999
• Est. Priority Date: 11/18/1996
• Status: Expired due to Fees

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Yeh, Wen-Kuan
• Primary Examiner(s): Chaudhari, Chandra
• Assistant Examiner(s): Berry, Renee R.
• Application Number:
  US08/772,880
• Time in Patent Office: 978 Days
• Field of Search: 437/190, 437/192, 438/626, 438/677, 438/763, 438/782, 438/713, 438/695, 438/303, 438/398, 438/649, 438/683, 438/655, 438/685
• US Class Current: 438/683
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A process of fabricating metal gate electrodes for MOS transistors included in semiconductor IC devices is disclosed. The process includes first providing a silicon substrate having formed over the surface thereof the field oxide layers and a gate dielectric layer defined in the transistor active region. A thin layer of silicon is then formed over the surface of the gate dielectric layer. A metal layer is then deposited over the surface of the gate dielectric layer by performing an LPCVD procedure in a gaseous environment containing silane and tungsten fluoride. The LPCVD procedure deposits tungsten over the surface of the silicon layer by reducing the tungsten fluoride into tungsten atoms while consuming the thin silicon layer to exhaustion. The gate structure in the active region is then formed by patterning in the metal layer, and the gate structure includes the metal gate electrode layer and the gate dielectric layer.

Claims

1. A process of fabricating a metal gate electrode layer for a metal-oxide semiconductor transistor in an integrated circuit device comprising the steps of:

providing a silicon substrate having a surface with field oxide layers and a gate dielectric layer formed over the surface to define a transistor active region;

forming a thin layer of silicon over a surface of said gate dielectric layer;

forming a metal layer over the surface of said gate dielectric layer by depositing a metal over the surface of said thin silicon layer, the formation of said metal layer completely consuming said thin silicon layer to exhaustion; and

forming a gate structure in said transistor active region by patterning, in said metal layer, said gate structure comprising a metal gate electrode layer and a gate dielectric layer.

2. The process of claim 1, wherein said metal layer is formed in a low-pressure chemical vapor deposition procedure.

3. The process of claim 2, wherein said low-pressure chemical vapor deposition procedure is performed at a temperature in the range of about 250 to 330°

C.

4. The process of claim 3, wherein said low-pressure chemical vapor deposition procedure is performed in a gaseous environment containing silane and tungsten fluoride.

5. The process of claim 4, wherein said silicon substrate is a P-type substrate.

6. The process of claim 4, wherein said silicon substrate is an N-type substrate.

7. The process of claim 4, wherein said gate dielectric layer is a silicon dioxide layer.

8. The process of claim 4, wherein said thin silicon layer is a monosilicon layer.

9. The process of claim 4, wherein said thin silicon layer is a polysilicon layer.

10. The process of claim 4, wherein said thin silicon layer is an epitaxial silicon layer.

11. The process of claim 4, wherein said thin silicon layer has a thickness in the range of about 100 to 250 Å

.

12. The process of claim 3, wherein said low-pressure chemical vapor deposition procedure is performed in a gaseous environment containing silane and aluminum fluoride.

22. The process of claim 1 wherein forming a metal layer over the surface of said gate dielectric further includes forming a metal layer on the surface of said gate dielectric.

13. A process of fabricating the metal gate electrode layer for a metal-oxide semiconductor transistor in an integrated circuit device comprising the steps of:

providing a silicon substrate having a surface with field oxide layers and a gate dielectric layer formed over the surface to define a transistor active region;

forming a thin layer of silicon over a surface of said gate dielectric layer;

forming a metal layer over the surface of said gate dielectric layer by performing a low-pressure chemical vapor deposition procedure in a gaseous environment containing silane and tungsten fluoride, said low-pressure chemical vapor deposition procedure depositing tungsten over the surface of said silicon layer by reducing said tungsten fluoride into tungsten atoms while completely consuming said thin silicon layer to exhaustion; and

forming a gate structure in said transistor active region by patterning, in said metal layer, said gate structure comprising a metal gate electrode layer and a gate dielectric layer.

14. The process of claim 13, wherein said low-pressure chemical vapor deposition procedure is performed at a temperature of about 250 to 330°

C.

15. The process of claim 14, wherein said silicon substrate is a P-type substrate.

16. The process of claim 14, wherein said silicon substrate is an N-type substrate.

17. The process of claim 14, wherein said gate dielectric layer is a silicon dioxide layer.

18. The process of claim 14, wherein said thin silicon layer is a monosilicon layer.

19. The process of claim 14, wherein said thin silicon layer is a polysilicon layer.

20. The process of claim 14, wherein said thin silicon layer is an epitaxial silicon layer.

21. The process of claim 14, wherein said thin silicon layer has a thickness in the range of about 100 to 250 Å

.

23. The process of claim 13 wherein forming a metal layer over the surface of said gate dielectric further includes forming a metal layer on the surface of said gate dielectric.