Shared intervention protocol for SMP bus using caches, snooping, tags and prioritizing

• US 5,946,709 A
• Filed: 04/14/1997
• Issued: 08/31/1999
• Est. Priority Date: 04/14/1997
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi Kumar, Lewis, Jerry Don, Dodson, John Steven, Kaiser, John Michael
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): Langjahr, David
• Application Number:
  US08/839,479
• Time in Patent Office: 869 Days
• Field of Search: 711/108, 711/143, 711/146, 711/173, 711/119
• US Class Current: 711/119
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a plurality of caches, one cache is identified as a specific cache which contains an unmodified copy of the value that was most recently read, and that cache is marked as containing the most recently read copy, while the remaining caches are marked as containing shared, unmodified copies of the value. When a requesting processing unit issues a message indicating that it desires to read the value, the specific cache transmits a response indicating that it cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The specific cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead. Since the cache latency can be much less than the memory latency, the read performance can be substantially improved with this new protocol.

Claims

1. A method of reducing memory latency associated with a read-type operation issued by a requesting processing unit in a multiprocessor computer system, the computer system including a plurality of processing units each having an associated cache, comprising the steps of:

loading a value from an address of a memory device into a plurality of caches;

identifying a specific cache of the plurality of caches which contains an unmodified copy of the value that was most recently read;

marking the specific cache as containing a most recently read, unmodified copy of the value;

marking the plurality of caches, except the specific cache, as containing shared, unmodified copies of the value;

issuing a message from a requesting processing unit indicating that the requesting processing unit desires to read the value from the address of the memory device; and

transmitting a response from the specific cache indicating that the specific cache can source the value.

2. The method of claim 1 wherein the response is detected by system logic and further comprising the step of forwarding the response from the system logic to the requesting processing unit.

3. The method of claim 1 further comprising the step of the specific cache sourcing the value to an interconnect which is connected to the requesting processing unit.

4. The method of claim 1 wherein the response is transmitted in response to the further step of the specific cache snooping the message from an interconnect which is connected to the requesting processing unit.

5. The method of claim 1 further comprising the step of tagging the message with a request identifier.

6. The method of claim 1 wherein:

the memory device detects the message; and

the response informs the memory device that the value is to be sourced by one of the plurality of caches.

7. The method of claim 1 wherein:

at least one other cache besides the specific cache transmits another response;

a first priority value is associated with the response from the specific cache; and

a second priority value is associated with the other response, the second priority value indicating a lower priority than the first priority value.

8. The method of claim 5 further comprising the step of the specific cache sourcing the value as a reply to an interconnect which is connected to the requesting processing unit, the reply being tagged with the request identifier.

9. A computer system comprising:

a memory device;

an interconnect connected to said memory device;

a plurality of processing units connected to said interconnect, each processing unit having a cache for storing values from said memory device, a given one of said caches further having means for indicating when said given cache contains a most recently read, unmodified copy of a value loaded from said memory device which value has also been contained as a shared, unmodified copy in at least one other of said caches; and

means for transmitting a response from said given cache indicating that said given cache can source the value loaded from said memory device to a processing unit requesting to read the value.

10. The computer system of claim 9 further comprising a system control point unit connected to said interconnect, said system control point unit having means for detecting said response and forwarding said response to said requesting processing unit.

11. The computer system of claim 9 further comprising means for sourcing the value from said given cache to said requesting processing unit.

12. The computer system of claim 9 wherein each said cache includes means for snooping said interconnect for a message from said requesting processing unit.

13. The computer system of claim 9 further comprising means for determining a priority associated with said response.

14. The computer system of claim 12 further comprising means for tagging said message with a request identifier.

15. The computer system of claim 12 wherein said memory device detects said message, and further comprising means for informing said memory device that the value is to be sourced by said given cache.

16. The computer system of claim 14 further comprising means for sourcing the value as a reply, said reply being tagged with said request identifier and an additional signal that the value is being sourced from a cache and not from the said memory device.