System for flushing queued memory write request corresponding to a queued read request and all prior write requests with counter indicating requests to be flushed

• US 5,948,081 A
• Filed: 12/22/1997
• Issued: 09/07/1999
• Est. Priority Date: 12/22/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Foster, Joseph E.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): WANG, ALBERT C
• Application Number:
  US08/995,367
• Time in Patent Office: 624 Days
• Field of Search: 345/501, 345/505, 395/182.11, 395/292, 395/859, 711/100, 711/151, 711/156, 710/5, 710/6, 710/25, 710/40, 710/26, 710/35, 710/39, 710/52, 710/58
• US Class Current: 710/40
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

A computer is provided having a bus interface unit between a CPU bus and a memory bus. The bus interface unit includes a memory controller and a read/write queue manager. The memory controller dispatches, or removes read requests or write requests from respective read or write requests queues depending on various modes of operation. Typically, the read requests are dispatched or removed either singularly or as a programmed series of read requests prioritized over write requests unless the write request queue is almost full. If the write request queue is almost full, then write request are removed either singularly or in a series before servicing the read request queue. The number of read or write request being removed from their respective queues can be programmed within a configuration register operably coupled to a controller arranged between the read and write request queues. The memory controller determines how many requests will be serviced within possibly a lengthy series of requests. By dispatching like requests (a series of reads followed by a series of writes, etc.) memory bus efficiency and/or pipelining is greatly improved.

Claims

1. A computer system, comprising:

a memory requestor;

a memory;

an interface unit coupled between said memory requestor and said memory, wherein said interface unit comprises;

a first request queue having a first plurality of storage locations;

a second request queue having a second plurality of storage locations;

a queue controller coupled between the first and second request queues to determine, during operation, when a current memory request dispatched from the memory requestor to the second plurality of storage locations is at the same memory address as a previous memory request stored within the first plurality of storage locations;

a memory controller coupled to the queue controller for flushing to the memory the previous memory request and any memory requests loaded prior in time before servicing the current memory request; and

wherein said first plurality of storage locations are ordered from a top of the first request queue to a bottom of the first request queue, and wherein the second request queue includes a counter associated with said current request queue containing a value dependent upon a location at which said previous memory request is relative to the top of the first request queue.

2. The computer system as recited in claim 1, further comprising a memory bus operably coupled between said interface unit and said memory.

3. The computer system as recited in claim 2, wherein said memory requestor comprises a device adapted to periodically obtain mastership of said memory bus.

4. The computer system as recited in claim 1, wherein said memory requester comprises a microprocessor.

5. The computer system as recited in claim 1, wherein said memory requestor comprises a peripheral device coupled to a peripheral component interface (PCI) bus operably linked to said interface unit.

6. The computer system as recited in claim 1, wherein said memory requester comprises a graphics accelerator device coupled to an advanced graphics port (AGP) bus operably linked to said interface unit.

7. The computer system as recited in claim 1, wherein said memory controller is adapted to receive a control signal forwarded from the queue controller for flushing a sequence of n memory requests stored within the first plurality of storage locations before servicing a single memory request stored within the second plurality of storage locations.

8. The computer system as recited in claim 1, wherein said memory controller is adapted to receive a control signal from the queue controller for flushing a sequence of memory requests stored within the second plurality of storage locations before servicing a single memory request stored within the first plurality of storage locations.

9. The computer system as recited in claim 1, wherein the value is decremented each time a memory request is removed from the first queue.

10. The computer system as recited in claim 9, wherein a series of memory requests are flushed from the first plurality of storage locations prior to servicing the current memory request if the decremented value of each of the series of memory requests is equal to zero.

11. The computer system as recited in claim 10, wherein the series of memory requests consists of n.

12. The computer system as recited in claim 11, wherein the n series of memory requests are flushed from the first plurality of storage locations containing a decremented value equal to zero immediately prior to servicing another n series of memory request from the second plurality of storage locations containing a decremented value equal to zero.

13. The computer system as recited in claim 11, wherein n programmably varies between one and three.

14. The computer system as recited in claim 13, further comprising a configuration register operably coupled to the memory controller for receiving a programmable bit indicative of the value of n.

15. A method for programmably bursting a series of memory requests from a memory queue manager to a memory, comprising:

providing a first request queue and a second request queue within the memory queue manager, each of which contain a plurality of memory requests;

setting a burst mode within a configuration register operably coupled to a memory controller;

snooping for a hit of a current memory request dispatched to the second request queue of a similar addressed previous memory request stored within the first request queue;

servicing a programmed n number of memory requests from the first request queue preceeding the previous memory request prior to servicing the previous memory request and the current memory request; and

assigning a count value to the current memory request dependent upon the location of the previous memory request within the first request queue.

16. The method as recited in claim 15, wherein said servicing comprises priority removing n number of memory request from said first request queue if the first request queue is substantially full before removing n number of memory request from the second request queue.

17. The method as recited in claim 16, further comprising:

assigning a count value to the current memory request dependent upon the location of the previous memory request within the first request queue; and

decrementing the count value each time a memory request is serviced from the first request queue.

18. The method as recited in claim 15, further comprising:

decrementing the count value each time a memory request is serviced from the first request queue.