System for flushing queued memory write request corresponding to a queued read request and all prior write requests with counter indicating requests to be flushed
First Claim
1. A computer system, comprising:
- a memory requestor;
a memory;
an interface unit coupled between said memory requestor and said memory, wherein said interface unit comprises;
a first request queue having a first plurality of storage locations;
a second request queue having a second plurality of storage locations;
a queue controller coupled between the first and second request queues to determine, during operation, when a current memory request dispatched from the memory requestor to the second plurality of storage locations is at the same memory address as a previous memory request stored within the first plurality of storage locations;
a memory controller coupled to the queue controller for flushing to the memory the previous memory request and any memory requests loaded prior in time before servicing the current memory request; and
wherein said first plurality of storage locations are ordered from a top of the first request queue to a bottom of the first request queue, and wherein the second request queue includes a counter associated with said current request queue containing a value dependent upon a location at which said previous memory request is relative to the top of the first request queue.
4 Assignments
0 Petitions
Accused Products
Abstract
A computer is provided having a bus interface unit between a CPU bus and a memory bus. The bus interface unit includes a memory controller and a read/write queue manager. The memory controller dispatches, or removes read requests or write requests from respective read or write requests queues depending on various modes of operation. Typically, the read requests are dispatched or removed either singularly or as a programmed series of read requests prioritized over write requests unless the write request queue is almost full. If the write request queue is almost full, then write request are removed either singularly or in a series before servicing the read request queue. The number of read or write request being removed from their respective queues can be programmed within a configuration register operably coupled to a controller arranged between the read and write request queues. The memory controller determines how many requests will be serviced within possibly a lengthy series of requests. By dispatching like requests (a series of reads followed by a series of writes, etc.) memory bus efficiency and/or pipelining is greatly improved.
-
Citations
18 Claims
-
1. A computer system, comprising:
-
a memory requestor; a memory; an interface unit coupled between said memory requestor and said memory, wherein said interface unit comprises; a first request queue having a first plurality of storage locations; a second request queue having a second plurality of storage locations; a queue controller coupled between the first and second request queues to determine, during operation, when a current memory request dispatched from the memory requestor to the second plurality of storage locations is at the same memory address as a previous memory request stored within the first plurality of storage locations; a memory controller coupled to the queue controller for flushing to the memory the previous memory request and any memory requests loaded prior in time before servicing the current memory request; and wherein said first plurality of storage locations are ordered from a top of the first request queue to a bottom of the first request queue, and wherein the second request queue includes a counter associated with said current request queue containing a value dependent upon a location at which said previous memory request is relative to the top of the first request queue. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A method for programmably bursting a series of memory requests from a memory queue manager to a memory, comprising:
-
providing a first request queue and a second request queue within the memory queue manager, each of which contain a plurality of memory requests; setting a burst mode within a configuration register operably coupled to a memory controller; snooping for a hit of a current memory request dispatched to the second request queue of a similar addressed previous memory request stored within the first request queue; servicing a programmed n number of memory requests from the first request queue preceeding the previous memory request prior to servicing the previous memory request and the current memory request; and assigning a count value to the current memory request dependent upon the location of the previous memory request within the first request queue. - View Dependent Claims (16, 17, 18)
-
Specification