Opsistor image processor with a reference detector and a reference image

• US 5,949,064 A
• Filed: 11/25/1997
• Issued: 09/07/1999
• Est. Priority Date: 11/25/1996
• Status: Expired due to Fees

• Current Assignee: Alan Y. Chow
• Original Assignee: Alan Y. Chow
• Inventors: Chow, Alan Y., Chow, Vincent Y.
• Primary Examiner(s): LE, QUE TAN
• Application Number:
  US08/977,853
• Time in Patent Office: 651 Days
• Field of Search: 250/214 LS, 250/208.1, 250/214.1, 250/551, 348/222, 348/294, 348/311
• US Class Current: 250/214.0LS
• CPC Class Codes: H01L 31/08 in which radiation controls flow of current through the device, e.g. photoresistors
• CPC Class Codes: H04B 10/032 using working and protection systems H04J14/0287 takes precedence
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 3/1506 with addressing of the image-sensor elements H04N3/1575 takes precedence
• CPC Class Codes: H04N 3/1512 for MOS image-sensors, e.g. MOS-CCD H04N3/1581 takes precedence
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An image processing system for capturing and compressing images into a digital format is disclosed. The system has an array of imaging pixel elements which consist of two photodiode detectors (Opsistor). One photodiode detector is a capture detector while the other detector is a reference detector. The capture detector has an anode electrically coupled to the cathode of the reference detector. The cathode of the capture detector is electrically coupled to the anode of the reference detector. An image may be compared to a reference image detected by the reference detector. Different levels of light between the captured image and the reference image change the electrical output of the opsistor. Image compression is facilitated since only pixel elements which change from frame to frame need be stored. Additionally, a processing and compression circuit may use column and row scans to eliminate unchanged pixels and store only pixels with different light levels between images.

Claims

1. An image processing system for capturing and compressing a series of images from an image source, the system comprising:

an image array having at least one pixel element, each pixel element having;

a capture photo detector having an anode and a cathode, the capture detector in exposure to the image source;

a reference photo detector having an anode, a cathode, the anode of the reference detector being electrically coupled to the cathode of the capture photo detector, and cathode of the reference detector being electrically coupled to the anode of the capture detector;

a light emitter array having at least one light emitter corresponding to each pixel element, wherein the light emitter emits light on the reference detector; and

a processing circuit electrically coupled to each pixel element and each light emitter, the processing circuit projecting a reference image from the light emitter on the reference detector and comparing the reference image with the image sensed by the capture detector.

2. The image processing system of claim 1 wherein the processing circuit includes a difference circuit for each pixel element, the difference circuit producing a difference signal indicative of the difference between the reference image projected on the reference detector and the image sensed by the capture detector.

3. The image processing system of claim 2 wherein the difference circuit further comprises:

a switch for each pixel element coupled to the cathode of the capture detector and the anode of the reference detector;

an amplifier for each pixel element with a gate coupled to the switch, a source coupled to the light emitter, and a drain coupled to a voltage source;

a sample and hold capacitor coupled to the cathode of the capture detector and the anode of the reference detector, the capacitor holding a value of a previous image to serve as the reference image; and

an error amplifier having an input coupled to a reference source and an input coupled to the cathode of the capture detector and the anode of the reference detector, and which outputs the difference signal when the switch is closed.

4. The image processing system of claim 2 further comprising an analog to digital converter coupled to the processing circuit, producing a digital value of the difference signal.

5. The image processing system of claim 4 wherein the analog to digital converter uses the difference signal to determine a first approximation of the digital value.

6. The image processing system of claim 4 further comprising:

a processor coupled to the analog to digital converter, the processing circuit forming digital representations of the series of images; and

a storage device coupled to the processing circuit which stores a digital representation of the series of images.

7. The image processing system of claim 1 wherein the anode of the capture detector and the cathode of the reference detector are coupled to a common voltage reference.

8. The image processing system of claim 2 wherein each pixel element is arranged in a row and a column in the array, the processing circuit further comprising:

a comparator coupled to the difference circuit of each pixel;

a change of state column line coupled to the comparator of each pixel element in a column;

a change of state row line coupled to the comparator of each pixel element in a row; and

wherein the comparator sets the state column line and state row line coupled to the pixel element low if the magnitude of the difference signal for the pixel element exceeds a validation level.

9. The image processing system of claim 8 wherein the processing circuit further comprises:

a summing circuit coupled to the change of state row lines and the change of state column lines; and

wherein the processing circuit is coupled to the summing circuit to determine particular rows of pixel elements and columns of pixel elements where the image sensed by the capture detector has changed from the reference image.

10. The image processing system of claim 8 wherein the processing circuit further comprises:

a row select circuit coupled to the change of state row lines;

a column select circuit coupled to the change of state column lines; and

wherein the processing circuit reads the difference signal of a pixel element by the row select circuit and the column select circuit.

11. The imaging system of claim 1 wherein the light emitters are light emitting diodes.

12. The imaging system of claim 1 further comprising an infra-red waveband filter between the capture detector and the image area.

13. The imaging system of claim 1 further comprising an ultra-violet waveband filter between the capture detector and the image area.

14. The imaging system of claim 1 further comprising:

a filter passing light at a first waveband between the capture detector and the image area; and

wherein each pixel element further comprises;

a second capture photo detector having an anode, a cathode, the second capture detector in exposure to the image source;

a second reference photo detector having an anode, a cathode, the anode of the second reference detector being electrically coupled to the cathode of the second capture detector, and the cathode of the reference detector being electrically coupled to the anode of the second capture detector; and

a second filter for light at a second waveband between the second capture detector and the image area;

a third capture photo detector having an anode, a cathode, the third capture detector in exposure to the image source;

a third reference photo detector having an anode, a cathode, the anode of the third reference detector being electrically coupled to the cathode of the third capture detector, and cathode of the third reference detector being electrically coupled to the anode of the third capture detector.

15. The image processing system of claim 14 wherein the first waveband is the red spectrum of visible light;

the second waveband is the green spectrum of visible light; and

the third waveband is the blue spectrum of visible light.

16. The image processing system of claim 1 wherein the image array is fabricated on a monolithic substrate having a front and rear surface.

17. The image processing system of claim 16 wherein the monolithic substrate is N-type silicon;

wherein the anode of the capture detector is a P+ doped region on the front surface of the substrate; and

wherein the cathode of the capture detector is a N+ doped region on the rear surface of the substrate opposite the P+ doped region of the capture detector; and

wherein the a node of the reference detector is a P+ doped region on the rear surface of the substrate; and

wherein the cathode of the reference detector is a N+ doped region on the front surface of the substrate opposite the P+ doped region of the reference detector.

18. The image processing system of claim 17 further comprising:

a front conductor layer in contact with the anode of the capture detector;

a front metal layer in contact with the N+ doped region of the capture detector and the front conductor layer;

a rear conductor layer in contact with the anode of the reference detector;

a rear metal layer in contact with the N+ doped region of the reference detector and the rear conductor layer.

19. The image processing system of claim 18 wherein the rear and front conductor layers are metal.

20. The image processing system of claim 18 wherein the rear and front conductor layers are transparent.

21. The image processing system of claim 20 wherein the rear and front conductor layers are indium tin oxide.

22. The image processing system of claim 17 further comprising:

a support substrate having a front surface;

a series of bumps in contact between the front surface of the support substrate and the rear surface of the monolithic substrate providing optical isolation between the adjacent reference detectors of each pixel elements; and

wherein the light emitter array is fabricated on the front surface of the support substrate surface.

23. The image processing system of claim 22 wherein the processing circuit is fabricated on the support substrate.

24. The image processing system of claim 23 wherein the bumps are conductors providing electrical connection between the processing circuit and the cathode of the capture detector.

25. The image processing system of claim 23 wherein the bumps are indium.

26. The image processing system of claim 1 further comprising:

a middle substrate;

a front substrate having a front surface facing the image area and a rear surface facing the middle substrate wherein the capture detector is fabricated on the front substrate; and

a rear substrate having a front surface facing the middle substrate and a rear surface facing the light emitter array, wherein the reference detector is fabricated on the rear substrate.

27. The image processing system of claim 26 wherein the processing circuit is fabricated in the middle substrate.

28. The image processing system of claim 26 wherein the front and rear substrates are N-type silicon,

wherein the anode of the capture detector is a P+ doped region formed on the front surface of the front substrate;

wherein the cathode of the capture detector is an N+ doped region on the rear surface of the front substrate opposite the P+ doped region of the capture detector;

wherein the anode of the reference detector is a P+ doped region formed on the rear surface of the rear substrate; and

wherein the anode of the reference detector is a N+ doped region on the front surface of the rear substrate opposite the P+ doped region of the reference detector.

29. The image processing system of claim 28 further comprising:

a front conductor layer in contact with the P+ doped region of the capture detector of each pixel element; and

a rear conductor layer in contact with the P+ doped region of the reference detector of each pixel element.

30. The image processing system of claim 29 further comprising:

a series of front bumps located between the rear surface of the front substrate and the middle substrate;

a series of rear bumps located between the front surface of the rear substrate and the middle substrate;

a series of conductive vias running through the middle substrate electrically coupling each rear bump with a front bump; and

wherein a front bump is in electrical contact with the N+ doped region of the capture detector and a rear bump is in electrical contact with the P+ doped region of the reference detector.

31. The image processing system of claim 30 wherein the bumps are indium and attached to the middle substrate and the front and rear substrates by flip chip bonding.

32. The image processing system of claim 30 further comprising:

an emitter substrate having the emitter array fabricated thereon; and

an aperture grid located between the emitter substrate and the rear surface of the rear substrate, wherein the aperture grid provides optical isolation between adjacent light emitters and the reference detector of each pixel element.

33. A method of capturing and compressing an image from an image source using an array of optical pixel elements producing a capture voltage level indicative of a captured image, the method comprising the steps of:

comparing the capture voltage signal of each pixel element with a reference voltage signal from the light level of a reference image;

determining a difference value between the capture voltage signal and the reference voltage signal;

determining the pixel elements where no change has occurred between the reference image and the captured image; and

storing the difference values associated with the pixel elements.

34. The method of claim 33 wherein each pixel element further comprises:

a capture photo detector having an anode and a cathode, the capture detector in exposure to the image source;

a reference photo detector having an anode, a cathode, the anode of the reference detector being electrically coupled to the cathode of the capture optical detector, and cathode of the reference detector being electrically coupled to the anode of the capture detector.

35. The method of claim 34 further comprising the step of storing the captured image for use as a reference image.

36. The method of claim 35 wherein a light emitter array having at least one light emitter corresponding to each pixel element is used to project the reference image.

37. The method of claim 33 further comprising the steps of:

converting the difference value into a digital value; and

storing the digital values as a representation of the captured images.

38. The method of claim 37 wherein the step of determining the pixel elements where no change has occurred between the reference image and the captured image further comprises:

coupling each pixel to a change of state row line and a change of state column line;

setting the change of state row line and change state column line low if any pixel on the row line or column line senses a change between the capture image and the reference image; and

summing the difference values from the pixels on the change of state row lines or the change of state column lines set low.

39. The method of claim 38 further comprising the steps of:

selecting the sum of difference values from a change of state row line or the change of state column line;

determining an average difference value the sum of difference values from the change of state row lines or the change of state column lines.

40. The method of claim 39 wherein the step of converting the difference value includes using the average difference value as a first approximation value to determine the digital value.

41. The method of claim 34 further comprising the step of coupling the anode of the capture detector and the cathode of the reference detector to a common voltage reference.