Semiconductor device having input protection circuit

• US 5,949,109 A
• Filed: 01/30/1997
• Issued: 09/07/1999
• Est. Priority Date: 11/30/1990
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation), Toshiba Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Wada, Masaharu, Numata, Kenji, Shimizu, Mitsuru, Fujii, Syuso
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/790,804
• Time in Patent Office: 950 Days
• Field of Search: 257/296, 257/355, 257/356, 257/357, 257/360, 257/361, 257/362, 257/363, 257/358
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

According to this invention, a well region is formed on a semiconductor substrate. An n⁺ -type first semiconductor region is formed in the well region, and an input pad for receiving an external signal is connected near the first semiconductor region. This input pad is connected to an input circuit of an integrated circuit constituted by an inverter circuit and to an external terminal for receiving an external signal. N⁺ -type second semiconductor regions are formed in the well region located on both sides of the first semiconductor region. A ground potential Vss is applied to these second semiconductor regions. A p⁺ -type third semiconductor region is formed around these second semiconductor regions in the well region. The ground potential is applied to the third semiconductor region. Therefore, a parallel circuit formed by a parasitic transistor and a parasitic diode is formed between the input pad and the ground potential. The parasitic transistor is turned on upon electrostatic discharge, and the parasitic diode is turned on when a negative potential for test is applied to the input pad, thereby preventing an erroneous operation of a transistor arranged on the semiconductor substrate.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a first well region of a second conductivity type formed in a first part of a surface region of said semiconductor substrate;

a memory circuit formed in said first well region;

a second well region of the second conductivity type formed in a second part of the surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said second well region, said first semiconductor region being connected to an input pad for receiving an external signal and to an input circuit for supplying the external signal to said memory circuit formed in said first well region;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in a part of the surface region of said second well region, said second semiconductor regions being connected to a ground potential; and

a third semiconductor region of the second conductivity type formed entirely within the surface region of said second well region and being connected to the ground potential, said third semiconductor region being arranged around said second semiconductor regions, a distance between said second and third semiconductor regions being larger than a distance between said first and second semiconductor regions.

2. A semiconductor device according to claim 1, further comprising:

a current path of a parasitic transistor being formed between said input pad and one of said second semiconductor regions connected to the ground potential, and a series circuit constituted by a parasitic diode and a parasitic resistor being formed between said input pad and said third semiconductor region connected to the ground potential.

3. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in a part of a surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region and connected to an input pad for receiving an external signal;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in a part of the surface region of said well region, said second semiconductor regions being connected to a ground potential;

a third semiconductor region of the second conductivity type formed entirely within the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions, a current path of a parasitic transistor being formed between said input pad and one of said second semiconductor regions connected to the ground potential, and a parasitic diode being formed between said input pad and said third semiconductor region; and

first and second resistor elements, one end of each of said first and second resistor elements being connected to said third semiconductor region, respectively, and the other end of each of said first and second resistor elements being connected to the ground potential,

wherein said well region includes no semiconductor region other than said first, second, and third semiconductor regions and is formed independently of other semiconductor circuits arranged in said semiconductor substrate.

4. A semiconductor device according to claim 3, further comprising:

a first wiring layer connected between said one end of said first resistor element and said third semiconductor region;

a second wiring layer connected between said one end of said second resistor element and said third semiconductor region;

a third wiring layer having first, second, third and fourth ends, said first end of said third wiring layer being connected to the other ends of said first and second resistor elements, said second and third ends of said third wiring layer being connected to said second semiconductor regions, respectively, and said fourth end of said third wiring layer being supplied with the ground potential.

5. A semiconductor device according to claim 3, wherein said first and second resistor elements are diffusion resistors.

6. A semiconductor device according to claim 3, wherein said first and second resistor elements are made of polysilicon.

7. A semiconductor device according to claim 3, wherein said third semiconductor region is supplied with a back gate bias potential through said first and second resistor elements.

8. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a memory cell array arranged in said semiconductor substrate;

a peripheral circuit, provided in the vicinity of said memory cell array, for controlling said memory cell array;

an input protection circuit connected to said peripheral circuit, said input protection circuit comprising a parasitic bipolar transistor and a parasitic diode;

a first generating circuit, provided in said semiconductor substrate, for generating a first back gate bias potential supplied to said parasitic diode of said input protection circuit, wherein the first back gate bias potential is set to be lower than ground potential; and

a second generating circuit, provided in said semiconductor substrate, for generating a second back gate bias potential supplied to said peripheral circuit.

9. A semiconductor device according to claim 8, wherein said input protection circuit includes:

a well region of a second conductivity type formed in a part of a surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region and connected to an input pad for receiving an external signal;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in a part of the surface region of said well region, said second semiconductor regions being connected to the ground potential; and

a third semiconductor region of the second conductivity type formed entirely within the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions,

wherein the first back gate bias potential is supplied to said third semiconductor region, and the second back gate bias potential is supplied to said semiconductor substrate.

10. A semiconductor device according to claim 9, wherein:

a current path of said parasitic bipolar transistor is formed between said input pad and one of said second semiconductor regions connected to the ground potential, and said parasitic diode is formed between said input pad and said third semiconductor region.

11. A semiconductor device according to claim 9, wherein the first and second back gate bias potentials are set to be equal to each other.

12. A semiconductor device according to claim 9, wherein the first and second back gate bias potentials are set at potentials different from each other.

13. A semiconductor device according to claim 12, wherein the first back gate bias potential is set at -2 to -3 volt.

14. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a first well region of a second conductivity type formed in a first part of a surface region of said semiconductor substrate and being connected to a first potential;

a memory circuit formed in said first well region;

a second well region of the second conductivity type formed in a second part of the surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said second well region, said first semiconductor region being connected to an input pad for receiving an external signal and to an input circuit for supplying the external signal to said memory circuit formed in said first well region;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in a part of the surface region of said second well region, said second semiconductor regions being connected to a second potential; and

a third semiconductor region of the second conductivity type formed entirely within the surface region of said second well region and being connected to the second potential, said third semiconductor region being arranged around said second semiconductor regions, a distance between said second and third semiconductor regions being larger than a distance between said first and second semiconductor regions,

wherein the first potential is a back gate bias potential, and the second potential is a ground potential.

15. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in a part of a surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region and connected to an input pad for receiving an external signal;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in a part of the surface region of said well region, said second semiconductor regions being connected to a first potential;

a third semiconductor region of the second conductivity type formed entirely within the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions, a current path of a parasitic transistor being formed between said input pad and one of said second semiconductor regions and a parasitic diode being formed between said input pad and said third semiconductor region; and

first and second resistor elements, one end of each of said first and second resistor elements being connected to said third semiconductor region, respectively, and the other end of each of said first and second resistor elements being connected to a second potential, wherein the first and second potentials are a ground potential.

16. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a well region of a second conductivity type formed in a part of a surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region and connected to an input pad for receiving an external signal;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in a part of the surface region of said well region, said second semiconductor regions being connected to a first potential;

a third semiconductor region of the second conductivity type formed entirely within the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions, a current path of a parasitic transistor being formed between said input pad and one of said second semiconductor regions and a parasitic diode being formed between said input pad and said third semiconductor region; and

first and second resistor elements, one end of each of said first and second resistor elements being connected to said third semiconductor region, respectively, and the other end of each of said first and second resistor elements being connected to a second potential,

wherein the first potential is a ground potential, and the second potential is a back gate bias potential, the back gate bias potential is set to be lower than the ground potential.

17. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a memory circuit formed in a first part of a surface region of said semiconductor substrate;

an input pad for receiving a signal;

an input circuit connected between said input pad and said memory circuit for supplying the signal to said memory circuit;

a well region of a second conductivity type formed in a second part of said surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region and connected only to said input pad and said input circuit;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in a part of the surface region of said well region, said second semiconductor regions being connected to a first potential; and

a third semiconductor region of the second conductivity type formed entirely within the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions and being connected to a second potential,

wherein said first semiconductor region, said well region, and one of said second semiconductor regions constitute a parasitic bipolar transistor,

wherein said first semiconductor region, said well region, and said third semiconductor region constitute a parasitic diode, and

wherein the first potential is a ground potential, the second potential is a back gate bias potential, and the back gate bias potential is set to be lower than the ground potential.

18. A semiconductor device according to claim 17, further comprising:

first and second resistor elements, one end of each of said first and second resistor elements being connected to said third semiconductor region, respectively, and the other end of said first and second resistor elements being connected to the second potential.

19. A semiconductor device according to claim 18, further comprising:

a first wiring layer connected between said one end of said first resistor element and said third semiconductor region;

a second wiring layer connected between said one end of said second resistor element and said third semiconductor region;

a third wiring layer having first, second, and third ends, said first and second ends of said third wiring layer being connected to said second semiconductor regions, respectively, and said third end of said third wiring layer being supplied with the ground potential; and

a fourth wiring layer having first and second ends, said first end being connected to the other ends of said first and second resistor elements, and said second end of said fourth wiring layer being supplied with the back gate bias potential.

20. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type connected to a first potential;

a memory circuit formed in a first part of a surface region of said semiconductor substrate;

an input pad for receiving a signal;

an input circuit connected to said input pad for supplying the signal to said memory circuit;

a well region of a second conductivity type formed in a second part of said surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region and connected only to said input pad and said input circuit;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in a part of the surface region of said well region, said second semiconductor regions being connected to a second potential; and

a third semiconductor region of the second conductivity type formed entirely within the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions and being connected to a third potential, a current path of a parasitic bipolar transistor being formed between said input pad and one of said second semiconductor regions and a parasitic diode being formed between said input pad and said third semiconductor region,

wherein the second potential is a ground potential, the third potential is a first back gate bias potential lower than the ground potential, and the first potential is a second back gate bias potential different from the first back gate bias potential.

21. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type;

a circuit formed on said semiconductor substrate;

an input pad for receiving a signal;

an input circuit connected between said input pad and said circuit for supplying the signal to said circuit;

a well region of a second conductivity type formed in said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in said well region and connected to said input pad and said input circuit;

second semiconductor regions of the first conductivity type respectively formed in said well region at opposing sides of said first semiconductor region, said second semiconductor regions being connected to a first potential; and

a third semiconductor region of the second conductivity type formed entirely within said well region, said third semiconductor region being arranged around said second semiconductor regions and being connected to a second potential,

wherein said first semiconductor region, said well region, and one of said second semiconductor regions constitute a parasitic bipolar transistor,

wherein said first semiconductor region, said well region, and said third semiconductor region constitute a parasitic diode, and

wherein the first potential is a ground potential, the second potential is a back gate bias potential, and the back gate bias potential is set to be lower than the ground potential.

22. A semiconductor device, comprising:

a first generating circuit for generating a first back gate bias potential, wherein the first back gate bias potential is set to be lower than ground potential;

a second generating circuit for generating a second back gate bias potential different than the first back gate bias potential;

a semiconductor substrate of a first conductivity type connected to the second back gate bias potential;

a memory circuit formed in a first part of a surface region of said semiconductor substrate;

an input pad for receiving a signal;

an input circuit connected to said input pad for supplying the signal to said memory circuit;

a well region of a second conductivity type formed in a second part of said surface region of said semiconductor substrate;

a first semiconductor region of the first conductivity type formed in a part of a surface region of said well region and connected to said input pad and said input circuit;

second semiconductor regions of the first conductivity type respectively formed at opposing sides of said first semiconductor region in a part of the surface region of said well region, said second semiconductor regions being connected to ground potential; and

a third semiconductor region of the second conductivity type formed entirely within the surface region of said well region, said third semiconductor region being arranged around said second semiconductor regions and being connected to the first back gate bias potential, a current path of a parasitic bipolar transistor being formed between said input pad and one of said second semiconductor regions and a parasitic diode being formed between said input pad and said third semiconductor region.