Digital phase detector and charge pump system reset and balanced current source matching methods and systems

• US 5,949,264 A
• Filed: 11/29/1996
• Issued: 09/07/1999
• Est. Priority Date: 11/29/1996
• Status: Expired due to Term

• Current Assignee: PLL Technologies, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Lo, Dennis C.
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US08/758,529
• Time in Patent Office: 1,012 Days
• Field of Search: 327/3, 327/7, 327/142, 327/146, 327/147, 327/156, 327/157, 331/1 A, 331/17
• US Class Current: 327/157
• CPC Class Codes: H03D 13/004 the logic means delivering pulses at more than one terminal, e.g. up and down pulses
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence

Abstract

A digital phase detector and charge pump circuit system reset circuit and method resets a digital phase detector according to the charge outputs between the charge pump circuits and a following loop filter. The sensing circuitry emulates portions of the circuitry of the digital phase detector and charge pump circuit system and minimizes deadband time. Current mirror portions of the charge pump circuit alternate between p-channel and n-channel devices to regularize output voltage levels produced by the charge pump circuit system.

Claims

1. In a digital phase detector and charge pump system, including a phase comparator having first and second output phase nodes at which adjustment pulses from said phase detector are provided, a charge pump circuit having first and second input nodes, for receiving the adjustment pulses from said phase comparator, said charge pump circuit having first and second output charge pump nodes at which the adjustment pulses are provided from said charge pump circuit, a sourcing and a sinking current source connected at a common node, and a capacitor connected to said common node, said first and second output charge pump nodes being connected to said sourcing and sinking current sources, a reset circuit for resetting said phase comparator comprising:

a first charging circuit having a first logical output node coupled to a first supply voltage through a first discharging switch, wherein said first charging circuit produces a first logical output at said first logical output node in response to said first output charge pump node, and said discharging switch is controlled by said first output phase node;

a second charging circuit having a second logical output node coupled to a second phase voltage through a second discharging switch, wherein said second charging circuit produces a second logical output at said second logical output node in response to said second output charge pump node, and said discharging switch is controlled by said second output phase node; and

a logic circuit having first and second inputs and a reset output, said first and second in puts connected respectively to said first and second logical output nodes, said logic circuit combining said first and second logical output nodes to produce a reset signal at said phase comparator.

2. In a digital phase detector and charge pump system, including a phase comparator having first and second output phase nodes at which adjustment pulses from said phase detector are provided, a charge pump circuit having first and second input nodes, for receiving the adjustment pulses from said phase comparator, said charge pump circuit having first and second output charge pump nodes at which the adjustment pulses are provided from said charge pump circuit, a sourcing and a sinking current source connected at a common node, and a 8 capacitor connected to said common node, said first and second output charge pump nodes being connected to said sourcing and sinking current sources, a reset circuit for resetting said phase comparator comprising:

a first charging circuit having a first logical output node coupled to a first supply voltage through a first discharging switch, wherein said first charging circuit produces a first logical output at said first logical output node in response to said first output charge pump node, and said discharging switch is controlled by said first output phase node;

a second charging circuit having a second logical output node coupled to a second supply voltage through a second discharging switch, wherein said second charging circuit produces a second logical output at said second logical output node in response to said second output charge pump node, and said discharging switch is controlled by said second output phase node; and

a logic circuit having first and second inputs and a reset output, said first and second inputs connected respectively to said first and second logical output nodes, said logic circuit combining said first and second logical output nodes to produce a reset signal at said phase comparator, wherein said first logical state detection circuit includes a current source, a capacitor, and a resistor.

3. In a digital phase detector and charge pump system, including a phase comparator having first and second output phase nodes at which adjustment pulses from said phase detector are provided, a charge pump circuit having first and second input nodes, for receiving the adjustment pulses from said phase comparator, said charge pump circuit having first and second output charge pump nodes at which the adjustment pulses are provided from said charge pump circuit, a sourcing and a sinking current source connected at a common node, and a capacitor connected to said common node, said first and second output charge pump nodes being connected to said sourcing and sinking current sources, a reset circuit for resetting said phase comparator comprising:

a first charging circuit having a first logical output node coupled to a first supply voltage through a first discharging switch, wherein said first charging circuit produces a first logical output at said first logical output node in response to said first out charge ump node, and said discharging switch is controlled by said first output phase node;

a second charging circuit having a second logical output node coupled to a second supply voltage through a second discharging switch, wherein said second charging circuit produces a second logical output at said second logical output node in response to said second output charge pump node, and said discharging switch is controlled by said second output phase node; and

a logic circuit having first and second inputs and a reset output, said first and second inputs connected respectively to said first and second logical output nodes, said logic circuit combining said first and second logical output nodes to produce a reset signal at said phase comparator, wherein said first logical state detection circuit includes a current source, a capacitor, and a resistor, wherein said current source is connected in parallel with said resistor and said capacitor.

4. In a digital phase detector and charge pump system, including a phase comparator having first and second output phase nodes at which adjustment pulses from said phase detector are provided, a charge pump circuit having first and second input nodes, for receiving the adjustment pulses from said phase comparator, said charge pump circuit having first and second output charge pump nodes at which the adjustment pulses are provided from said charge pump circuit, a sourcing and a sinking current source connected at a common node, and a capacitor connected to said common node, said first and second output charge pump nodes being connected to said sourcing and sinking current sources, a reset circuit for resetting said phase comparator comprising:

a first charging circuit having a first logical output node coupled to a first supply voltage through a first discharging switch, wherein said first charging circuit produces a first logical output at said first logical output node in response to said first output charge pump node, and said discharging switch is controlled by said first output phase node;

a second charging circuit having a second logical output node coupled to a second supply voltage through a second discharging switch, wherein said second charging circuit produces a second logical output at said second logical out node in response to said second output charge pump node, and said discharging switch is controlled by said second output phase node; and

a logic circuit having first and second inputs and a reset output, said first and second inputs connected respectively to said first and second logical output nodes, said logic circuit combining said first and second logical output nodes to produce a reset signal at said phase comparator, wherein said second logical state detection circuit includes a current source, a capacitor, and a resistor.

5. In a digital phase detector and charge pump system, including a phase comparator having first and second output phase nodes at which adjustment pulses from said phase detector are provided, a charge pump circuit having first and second input nodes, for receiving the adjustment pulses from said phase comparator, said charge pump circuit having first and second output charge pump nodes at which the adjustment pulses are provided from said charge pump circuit, a sourcing and a sinking current source connected at a common node, and a capacitor connected to said common node, said first and second output charge pump nodes being connected to said sourcing and sinking current sources, a reset circuit for resetting said phase comparator comprising:

a first charging circuit having a first logical output node coupled to a first supply voltage through a first discharging switch, wherein said first charging circuit produces a first logical output at said first logical output node in response to said first output charge pump node, and said discharging switch is controlled by said first output phase node;

a second charging circuit having a second logical output node coupled to a second supply voltage through a second discharging switch, wherein said second charging circuit produces a second logical output at said second logical output node in response to said second output charge pump node, and said discharging switch is controlled by said second output phase node; and

a logic circuit having first and second inputs and a reset output, said first and second inputs connected respectively to said first and second logical output nodes, said logic circuit combining said first and second logical output nodes to produce a reset signal at said phase comparator, wherein said second logical state detection circuit includes a current source, a capacitor, and a resistor, wherein said current source is connected in parallel with said resistor and said capacitor.

6. In a digital phase detector and charge pump system, including a phase comparator having first and second output phase nodes at which adjustment pulses from said phase detector are provided, a charge pump circuit having first and second input nodes, for receiving the adjustment pulses from said phase comparator, said charge pump circuit having first and second output charge pump nodes at which the adjustment pulses are provided from said charge pump circuit, a sourcing and a sinking current source connected at a common node, and a capacitor connected to said common node, said first and second output charge pump nodes being connected to said sourcing and sinking current sources, a reset circuit for resetting said phase comparator comprising:

a first charing circuit having a first logical output node coupled to a first supply voltage through a first discharging switch, wherein said first charging circuit produces a first logical output at said first logical output node in response to said first output charge pump node, and said discharging switch is controlled by said first output phase node;

a second charging circuit having a second logical output node coupled to a second supply voltage through a second discharging switch, wherein said second charging circuit produces a second logical output at said second logical output node in response to said second output charge pump node, and said discharging switch is controlled by said second output phase node; and

a logic circuit having first and second inputs and a reset output, said first and second inputs connected respectively to said first and second logical output nodes, said logic circuit combining said first and second logical output nodes to produce a reset signal at said phase comparator, wherein said first logical state detection circuit includes a current source, a capacitor, and a resistor.

7. In a digital phase detector and charge pump system, including a phase comparator having first and second output phase nodes at which adjustment pulses from said phase detector are provided, a charge pump circuit having first and second input nodes, for receiving the adjustment pulses from said phase comparator, said charge pump circuit having first and second output charge pump nodes at which the adjustment pulses are provided from said charge pump circuit, a sourcing and a sinking current source connected at a common node, and a a capacitor connected to said common node, said first and second output charge pump nodes being connected to said sourcing and sinking current sources, a reset circuit for resetting said phase comparator comprising:

a first charging circuit having a first logical output node coupled to a first supply voltage through a first discharging switch, wherein said first charging circuit produces a first logical output at said first logical output node in response to said first output charge pump node, and said discharging switch is controlled by said first is output phase node;

a second charging circuit having a second logical output node coupled to a second supply voltage through a second discharging switch, wherein said second charging circuit produces a second logical output at said second logical output node in response to said second output charge pump node, and said discharging switch is controlled by said second output phase node; and

a logic circuit having first and second inputs and a reset output, said first and second inputs connected respectively to said first and second logical output nodes, said logic circuit combining said first and second logical output nodes to produce a reset signal at said phase comparator, wherein said second logical state detection circuit includes a current source, a capacitor, and a resistor.

8. In a digital phase detector and charge pump system, including a phase comparator having first and second output phase nodes at which adjustment pulses from said phase detector are provided, a charge pump circuit having first and second input nodes, for receiving the adjustment pulses from said phase comparator, said charge pump circuit having first and second output charge pump nodes at which the adjustment pulses are provided from said charge pump circuit, a sourcing and a sinking current source connected at a common node, and a capacitor connected to said common node, said first and second output charge pump nodes being connected to said sourcing and sinking current sources, a reset circuit for resetting said phase comparator comprising:

a first charging circuit having a first logical output node coupled to a first supply voltage through a first discharging switch, wherein said first charging circuit produces a first logical output at said first logical output node in response to said first output charge pump node, and said discharging switch is controlled by said first output phase node;

a second charging circuit having a second logical output node coupled to a second supply voltage through a second discharging switch, wherein said second charging circuit produces a second logical output at said second logical output node in response to said second output charge pump node, and said discharging switch is controlled by said second output phase node; and

a logic circuit having first and second inputs and a reset output, said first and second inputs connected respectively to said first and second logical output nodes, said logic circuit combining said first and second logical output nodes to produce a reset signal at said phase comparator, wherein said second logical state detection circuit includes a current source, a capacitor, and a resistor.