Short circuit protection for parallel connected devices

• US 5,949,273 A
• Filed: 07/14/1997
• Issued: 09/07/1999
• Est. Priority Date: 07/12/1996
• Status: Expired due to Term

• Current Assignee: Semikron Elektronik GmbH & Company KG (Heilbronner Holding GbR)
• Original Assignee: Semikron Elektronik GmbH & Company KG (Heilbronner Holding GbR)
• Inventors: Mourick, Paul, Anderlohr, Erik, Schreiber, Dejan
• Primary Examiner(s): Wells, Kenneth B.
• Assistant Examiner(s): NGUYEN, MINH T
• Application Number:
  US08/890,638
• Time in Patent Office: 785 Days
• Field of Search: 327/403, 327/405, 327/432, 327/433, 327/473, 327/314, 327/325, 327/384, 327/440, 327/442, 327/110, 327/309, 327/313, 327/324, 307/126, 307/130, 361/56, 361/18, 361/78, 361/101, 361/63, 363/53, 363/85, 363/96, 363/132
• US Class Current: 327/442
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H03K 17/08128 in composite switches
• CPC Class Codes: H03K 17/12 Modifications for increasing the maximum permissible switched current
• CPC Class Codes: H03K 17/127 in composite switches

Abstract

A power semiconductor circuit provides a simple gate drive for switch components for the use in parallel-connected half-bridges, taking into consideration a gate voltage limitation to achieve short-circuit resistance. The circuit consists of drive circuits and main power circuits. The present invention contributes to solving the problems of the influence of the main power circuit on the drive circuit. According to the invention, switching transistors connected in parallel to the driver through separate activation and deactivation resistors, the former of relatively low resistance and the latter of relatively high resistance. Each of the switching transistors has an emitter resistor connected in parallel with a respective clamping diode to a sum point at ground, the cathode to the emitter. Each of the activation resistors is connected in series to the driver through a respective diode whose cathode is connected to the activation resistor. The gate of each switching transistor is connected to a supply voltage through a respective shunt diode with the cathode connected to the supply voltage to ensure that, due to the switching transistor'"'"'s internal capacitive reactions, no gate voltage increase occurs that is higher than the supply voltage of the driver stage. The diodes are connected in series with the activation resistors prevent equalization between the gate ports via these resistors. Fast epitaxial diodes should be preferred in the gate circuit because of their low parasitic capacitances.

Claims

1. A power semi-conductor circuit comprising:

a driver having an activation and deactivation output; and

a plurality of parallel connected switching circuits, each said switching circuit having;

a switching transistor having a gate, emitter and collector,

said emitter being connected to emitters of all other said switching circuits,

said collector being connected to collectors of all other said switching circuits,

an activation resistor connected between said gate and a cathode of a first diode, said first diode having an anode connected to said activation output,

a shunt diode having a cathode connected to a supply voltage and an anode connected to said gate,

a deactivation resistor connected between said deactivation output and said gate, and

an emitter resistor parallel connected to a clamping diode, said clamping diode having a cathode connected to said emitter and an anode connected to a sum point connected to ground;

such that during a short circuit condition, said switching circuit prevents oscillations in voltages from appearing at each respective gate, and also prevent mismatches in voltages from appearing across said emitter resistors.

2. A circuit according to claim 1, wherein each said activation resistor is of a lower impedance than each said deactivation resistor.

3. A circuit according to claim 1, wherein each said first, clamping, and shunt diodes are fast epitaxial diodes.

4. A circuit according to claim 1, wherein each said clamping diode is a Schottky diode.

5. A circuit as in claim 1, wherein:

each said first diode is a fast epitaxial diode; and

each said clamping diode is a Schottky diode.

6. A circuit as in claim 1, wherein:

each said first diode is a fast epitaxial diode;

each said clamping diode is a Schottky diode; and

each said activation resistor is of a lower impedance than each said deactivation resistor.

7. A circuit arrangement, comprising:

a driver having activation and deactivation outputs;

a plurality of switching transistors, each with a gate connected to said activation output of said driver through a respective diode in series with a respective activation resistor;

each of said switching transistors having an emitter connected to emitters of all other said switching transistors,

each of said switching transistors having a collector connected to collectors of all other said switching transistors,

each of said gates also being connected to said deactivation output of said driver through a respective deactivation resistor;

each of said switching transistors having an emitter connected to a sum point through a respective emitter resistor, each said respective emitter resistor being connected in parallel to a respective clamping diode;

each of said gates being connected to a supply voltage through a respective shunt diode, whereby voltages appearing at each respective gate are limited during a short circuit condition.

8. A circuit as in claim 7, wherein each said deactivation resistor has a resistance that is greater than a resistance of each said activation resistor.

9. A circuit as in claim 7, wherein:

said driver selectively connects said activation output to said supply voltage; and

said driver selectively connects said deactivation output to ground.

10. A circuit as in claim 7, wherein said sum point is at ground.

11. A circuit as in claim 7, wherein each said clamping diode is a Schottky diode.

12. A circuit as in claim 7, wherein:

each said deactivation resistor has a resistance that is greater than a resistance of each said activation resistor;

said driver selectively connects said activation output to said supply voltage; and

said driver selectively connects said deactivation output to ground.

13. A circuit as in claim 7, wherein:

each said deactivation resistor has a resistance that is greater than a resistance of each said activation resistor;

said driver selectively connects said activation output to said supply voltage;

said driver selectively connects said deactivation output to ground; and

sum point is at ground.

14. A circuit as in claim 7, wherein:

each said deactivation resistor has a resistance that is greater than a resistance of each said activation resistor;

said driver selectively connects said activation output to said supply voltage;

said driver selectively connects said deactivation output to ground; and

each said clamping diode is a Schottky diode.

15. A circuit as in claim 7, wherein:

each said deactivation resistor has a resistance that is greater than a resistance of each said activation resistor;

said driver selectively connects said activation output to said supply voltage;

said driver selectively connects said deactivation output to ground;

each said clamping diode is a Schottky diode; and

each said diode in series with said activation resistor is a fast epitaxial diode.

16. A power semi-conductor circuit comprising:

a driver having an activation and deactivation output;

a circuit with parallel connected switching circuits, each said switching circuit having;

a switching transistor having a gate, emitter and collector,

said emitter being connected to an emitter common point,

said collector being connected to a collector common point,

an activation resistor being series connected between said gate and a cathode of a first diode, said first diode having an anode connected to said activation output,

a shunt diode having a cathode connected to a supply voltage and an anode connected to said gate,

a deactivation resistor being connected between said deactivation output and said gate, and

an emitter resistor being parallel connected to a clamping diode, said clamping diode having a cathode connected to said emitter and an anode connected to a sum point connected to ground;

each said deactivation resistor has a resistance that is greater than a resistance of each said activation resistor,

said driver selectively connects said activation output to said supply voltage;

said driver selectively connects said deactivation output to ground;

each said clamping diode is a Schottky diode; and

each said diode in series with said activation resistor is a fast epitaxial diode.