Select line driver for a display matrix with toggling backplane

• US 5,949,398 A
• Filed: 04/12/1996
• Issued: 09/07/1999
• Est. Priority Date: 04/12/1996
• Status: Expired due to Term

• Current Assignee: Thomson Multimedia SA (Vantiva SA)
• Original Assignee: Thomson Multimedia SA (Vantiva SA)
• Inventors: Kim, Hongjin
• Primary Examiner(s): Hjerpe, Richard A.
• Assistant Examiner(s): CHANG, KENT WU
• Application Number:
  US08/631,484
• Time in Patent Office: 1,243 Days
• Field of Search: 345/87, 345/89, 345/94, 345/98, 345/100, 345/99, 345/92, 345/96, 377/78, 377/79, 377/75, 377/64
• US Class Current: 345/100
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

When a given row in an array of a liquid crystal display having a toggling backplane voltage is de-selected, the row select line voltage also toggles to prevent capacitive current in the pixel capacitance. The row select line driver includes a pair of transistors coupled in a push-pull configuration. The pair of transistors are responsive to a control signal that is produced in a corresponding stage of cascaded stages of a shift register. The pair of transistors form a buffer stage that prevents the toggling voltage developed in the row select line when the row is de-selected from affecting the operation of the shift register.

Claims

1. A display apparatus for applying brightness signals to pixels arranged in a plurality of rows and in a plurality of columns of an array, comprising:

a plurality of column drivers for developing said brightness signals at pixel electrodes of pixels of a given row when said given row is selected;

a source of a toggling, first signal developed in common electrodes of said pixels having, alternately, first and second levels with respect to a predetermined level of a given brightness signal;

a plurality of stages forming a row select scanner, a given one of said stages that is associated with said given row, including;

a first transistor for generating a row line select signal in a corresponding row line to select said given row, during a given row select interval; and

a second transistor coupled to said row line for developing a voltage in a capacitance associated with said row line, in accordance with said first signal, said capacitance capacitively coupling said first signal to said row line to develop a toggling row line de-select signal at said row line that is level shifted with respect to said first signal in accordance with said capacitance voltage, during a row de-select interval.

2. A display apparatus according to claim 1 wherein a difference between said row line de-select signal and said first signal is maintained constant at each of the levels of said first signal.

3. A display driver according to claim 1 wherein said second transistor develops said row line de-select signal at third and fourth levels when said first signal is at said first and second levels, respectively.

4. A display driver according to claim 1 wherein said first and second transistors operate in a push-pull configuration with respect to said row line.

5. An apparatus according to claim 1 wherein said row line select signal is at the same level with respect to said predetermined level of said given brightness signal when said first signal is at each of said first and second levels.

6. A row select line scanner for an array of a display apparatus, comprising:

a plurality of cascaded stages, a given one of said cascaded stages, including;

an input section responsive to an output pulse signal developed at an output of a second stage of said cascaded stages for generating a control signal of said given stage;

a first transistor responsive to said control signal for generating an output pulse signal of said given stage that is coupled to an input section of a third stage of said cascaded stages, said output pulse signal being time shifted with respect to said output pulse of said second stage to provide for a shift register operation; and

a switching network responsive to said control signal for generating in a given row line, during a row select interval, a row line select signal that is time shifted with respect to said output pulse of said second stage, and for generating in said given row line a toggling, row line de-select signal, during a row de-select interval, that is buffered and decoupled from said input section of said third stage.

7. A row select scanner according to claim 6 wherein said switching network comprises a second transistor coupled to said row line for generating said row select line signal and a third transistor coupled to said row line and to a source of a toggling, second signal for generating said row line de-select signal.

8. A row select scanner according to claim 7 wherein said second and third transistors are coupled in a push-pull configuration.

9. A row select scanner according to claim 7 wherein said control signal is stored in a capacitance that is coupled to a control terminal of each of said first and second transistors for conditioning each of said first and second transistors to conduction.

10. A row select scanner according to claim 7 further comprising, a fourth transistor responsive to an output pulse signal of a stage downstream of said given stage for disabling said first and second transistors, during said row de-select interval.

11. A row select scanner according to claim 6 further comprising, a source of a toggling, second signal developed in common electrodes of said pixels and having, alternately, first and second levels, wherein said switching network includes a second transistor coupled to said row line for developing a voltage in a capacitance associated with said row line, in accordance with said second signal, during a first portion of a row de-select interval, and wherein said capacitance capacitively couples said second signal to said row line to develop said toggling row line de-select signal in said row line that is level shifted with respect to said second signal in accordance with said capacitance voltage, during a second portion of said row de-select interval.

12. A row select scanner according to claim 11 wherein said capacitance voltage is replenished by the operation of said second transistor after each time said second signal toggles.

13. A row select scanner according to claim 11 wherein said capacitance voltage is replenished by the operation of said second transistor once in each row de-select interval.

14. A shift register for a row select scanner of a matrix display, comprising:

a source of a plurality of phase shifted clock signals;

a plurality of cascaded stages, a given one of said cascaded stages, including;

an input section responsive to an output pulse signal developed at an output of a second stage of said cascaded stages for generating a control signal;

a first transistor responsive to said control signal for generating an output pulse signal of said given stage that is coupled to an input section of a third stage, said control signal conditioning said first transistor to generate said output pulse signal of said given stage when a clock signal is developed at a main current conducting terminal of said first transistor such that said output pulse signal of said given stage is time-shifted with respect to said output signal of said second stage;

a second transistor responsive to said control signal for generating a row line select signal in a corresponding row line, said control signal conditioning said second transistor to generate said row line select signal when a clock signal is developed at a main current conducting terminal of said second transistor such that said row line select signal is time-shifted with respect to said output signal of said second stage; and

a third transistor coupled to said row line for generating in said row line a row de-select signal at a first level, during a first row de-select interval, and at a second level, during a second row de-select interval.