Accelerated graphics port multiple entry gart cache allocation system and method

• US 5,949,436 A
• Filed: 09/30/1997
• Issued: 09/07/1999
• Est. Priority Date: 09/30/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Collins, Michael J., Lester, Robert Allan, Jones, Phillip M., Johnson, Jerome J., Santos, Gregory N., Horan, Ronald T.
• Primary Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/941,861
• Time in Patent Office: 707 Days
• Field of Search: 345/501-506, 345/520, 345/521, 345/508, 345/511, 345/512, 345/203, 711/100, 711/117-122, 711/141-143, 711/200, 711/202, 711/203, 711/205-209, 711/221
• US Class Current: 345/501
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06T 1/60 Memory management

Abstract

A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. When a GART table entry is not found in the cache, a memory access is required to obtained the needed GART table entry. There are two GART table entries in each quadword returned in toggle mode of the cacheline of memory information returned from the memory read access. At least one quadword (two GART table entries) are stored in the cache each time a memory access is required because of a cache miss.

Claims

1. A computer system, comprising:

a processor executing software instructions and generating graphics data;

a main memory having an addressable memory space comprising a plurality of bytes of storage, wherein each of the plurality of bytes of storage has a unique address;

the software instructions and the graphics data being stored in some of the plurality of bytes of storage of said main memory, wherein the graphics data is stored in a plurality of pages of graphics data, each of the plurality of pages of graphics data comprising a number of the plurality of bytes of storage;

a graphics processor generating video display data from the graphics data and adapted for connection to a video display to display the video display data;

a first interface logic for connecting said processor to said main memory;

a second interface logic for connecting said processor and said main memory to said graphics processor;

said second interface logic having a cache memory for storing a plurality of 32 bit wide GART table entries;

a graphics address remapping table (GART table) having a plurality of 32 bit entries, each of the plurality of GART table entries comprising an address pointer to a corresponding main memory address of each of the plurality of pages of graphics data, the plurality of GART table entries being stored in some other of the plurality of bytes of storage of said main memory and each of the plurality of GART table entries being associated with a block of graphics device addresses; and

said graphics processor requesting a graphics data transaction by asserting a graphics device address to said second interface logic, wherein said second interface logic determines if a required one of the plurality of GART table entries is stored in said cache memory;

if the required one of the plurality of GART table entries is stored in said cache memory then said second interface logic uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to a corresponding address of a one of the plurality of pages of graphics data stored in said main memory;

if the required one of the plurality of GART table entries is not stored in said cache memory, then said second interface logic reads at least two of the plurality of GART table entries from said main memory, wherein one of the at least two being the required one of the plurality of GART table entries needed for address translation and the at least two of the plurality of GART table entries are quadword aligned; and

said second interface logic stores the quadword aligned at least two of the plurality of GART table entries in said cache memory, and uses the required one of the plurality of GART table entries to translate the graphics device address of the requested graphics data transaction to the corresponding address of the one of the plurality of pages of graphics data stored in said main memory.

2. The computer system of claim 1, wherein said second interface logic reads a cacheline of the plurality of GART table entries from said main memory, the cacheline containing the required one.

3. The computer system of claim 2, wherein the cacheline comprises a plurality of quadwords, each of the quadwords comprising two of the plurality of GART table entries.

4. The computer system of claim 3, wherein the required one is in a first quadword of the plurality of quadwords returned in toggle mode during reading of the plurality of GART table entries from said main memory.

5. The computer system of claim 4, further comprising said second interface logic storing in said cache memory the plurality of GART table entries contained in the plurality of quadwords of the cacheline.

6. The computer system of claim 2, wherein the cacheline is four quadwords.

7. The computer system of claim 1, further comprising a third interface logic for connecting said processor and said main memory to input-output devices.

8. The computer system of claim 1, further comprising a fourth interface logic for connecting said processor and said main memory to storage devices.

9. The computer system of claim 1, wherein the plurality of GART table entries are stored in a plurality of pages of GART table entries in said system memory.

10. The computer system of claim 9, wherein the plurality of pages of GART table entries are stored in said system memory in a non-contiguous and random order.

11. The computer system of claim 10, further comprising a GART directory having a plurality of entries, each of the plurality of GART directory entries comprising an address pointer to a corresponding one of the plurality of pages of GART table entries, wherein said second interface logic uses the plurality of GART directory entries for locating the plurality of pages of GART table entries in said main memory.

12. The computer system of claim 1, wherein the number of the plurality of bytes of storage in each of the plurality of pages of graphics data is 4096 bytes.

13. The computer system of claim 1, wherein the processor is a plurality of processors.

14. The computer system of claim 1, further comprising a video display.

15. The computer system of claim 1, wherein the plurality of pages of graphics data are stored in said random access memory in a non-contiguous and random order.

16. The computer system of claim 15, wherein each one of the plurality of pages of graphics data is associated with the each one of the plurality of GART table entries such that a first number of most significant bits of the plurality of binary bits comprise a base address of the associated each one of the plurality of pages of graphics data.

17. The computer system of claim 1, further comprising a network interface card, a hard disk, a floppy disk drive, a modem, a keyboard and a mouse.

18. The computer system of claim 1, further comprising a serial port, a parallel port and a real time clock.

19. The computer system of claim 1, further comprising a read only memory basic input-output system (ROM BIOS), a non-volatile random access memory (NVRAM), a tape drive and a CD ROM drive.

20. A method, in a computer system, of caching at least two of a plurality of graphics address remapping table (GART table) entries stored the computer system memory, said method comprising the steps of:

storing a plurality of pages of graphics data in any order in a computer system memory;

storing a plurality of entries of a graphics address remapping table (GART table) in the computer system memory, wherein each one of the plurality of GART table entries comprises 32 bits, corresponds to a one of the plurality of pages of graphics data stored in the computer system memory and is used for translating graphics device addresses to corresponding addresses of the plurality of pages of graphics data in the computer system memory;

translating a graphics device address of a graphics data transaction request by determining if a required one of the plurality of GART table entries is stored in a cache memory of the computer system;

if the required one is stored in the cache memory then using the required one for translating the graphics device address to a corresponding address of a one of the plurality of pages of graphics data stored in the system memory;

if the required one is not stored in the cache memory then reading at least two of the plurality of GART table entries stored in the computer system memory, wherein one of the at least two being the required one of the plurality of GART table entries needed for address translation and the at least two of the plurality of GART table entries are quadword aligned; and

storing the quadword aligned at least two of the plurality of GART table entries read from the computer system memory into the cache memory then using the required one for translating the graphics device address to the corresponding address of the one of the plurality of pages of graphics data stored in the system memory.

21. The method of claim 20, wherein the step of reading the at least two of the plurality of GART table entries comprises the step of reading a cacheline of the plurality of GART table entries from the system memory, the cacheline containing the required one.

22. The method of claim 21, wherein the cacheline comprises a plurality of quadwords, each of the quadwords comprising two of the plurality of GART table entries.

23. The method of claim 22, wherein the required one is in a first quadword of the plurality of quadwords returned in toggle mode during the step of reading the cacheline of the plurality of GART table entries from the system memory.

24. The method of claim 23, further comprising the step of storing in the cache memory the plurality of GART table entries contained in the plurality of quadwords of the cacheline.