Schematic design entry with annotated timing

• US 5,949,690 A
• Filed: 09/26/1997
• Issued: 09/07/1999
• Est. Priority Date: 09/26/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lawman, Gary R.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/938,208
• Time in Patent Office: 711 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/468.28, 364/578
• US Class Current: 716/102
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing

Abstract

The invention provides to the user a way of ascertaining the estimated delay through a circuit, by placing a timing attribute on the schematic symbol for the circuit that automatically displays the estimated delay. Reported delays may include maximum delay, typical delay, and/or minimum delay on the critical path. In a first embodiment, the schematic entry software consults a macro speeds file to obtain delay information for the macro. In a second embodiment, the macro delay information is added to the standard device speeds file. In a third embodiment, the symbol file (or other file) for the macro includes a formula for the critical path delay through the macro, based on the delays in the standard device speeds file. The schematic entry software therefore uses the standard device speeds file to calculate the macro delay. According to a second aspect of the invention, schematic-entry software accepts pointer-driven (e.g., mouse-driven) input designating starting and ending points on a path, and reports the path delay between these points. According to a third aspect of the invention, schematic-entry software accepts pointer-driven input designating a group of schematic symbols and reports the path delay on the critical paths through the circuit comprising the designated symbols.

Claims

1. A method for displaying a macro symbol, the method comprising the steps of:

a) receiving a command to display the macro symbol; and

b) displaying the macro symbol along with a multiplicity of associated delays,

wherein the displayed delays comprise delays for the same path through the macro under different operating conditions.

2. The method of claim 1 wherein the displayed delays comprise minimum and typical delays.

3. A method for displaying a macro symbol, the method comprising the steps of:

a) receiving a command to display the macro symbol; and

b) displaying the macro symbol along with a multiplicity of delays,

wherein the displayed delays comprise delays for the same circuit implemented in different FPGAs.

4. The method of claim 3 wherein the displayed delays comprise delays for the same circuit implemented in FPGAs with different speed grades.

5. A method for displaying a macro symbol representing an FPGA circuit comprising blocks and nets, the method comprising the steps of:

a) receiving a command to display the macro symbol; and

b) displaying the macro symbol along with a multiplicity of delays,

wherein the displayed delays comprise separately displayed block delays and net delays.

6. A method for annotating timing information onto a schematic, the method comprising the steps of:

a) receiving a command to display a macro symbol;

b) reading a timing formula corresponding to the macro symbol, the timing formula representing a macro delay in terms of delays included in a device speeds file;

c) retrieving relevant device delays for a plurality of target FPGAs from the device speeds file;

d) calculating a plurality of macro delays for the plurality of target FPGAs based on the timing formula and the delays retrieved from the device speeds file; and

e) displaying the plurality of macro delays along with the macro symbol.

7. The method of claim 6, wherein the timing formula is read from the file storing the display information for the symbol.

8. A method for displaying a macro symbol, the method comprising the steps of:

a) designating one of a group of available macro delays to be displayed;

b) receiving a command to display the macro symbol; and

c) displaying the macro symbol alone with the designated delay,

wherein the group of available macro delays comprises delays for the same circuit implemented in different FPGAs.

9. The method of claim 8 wherein the group of available macro delays comprises delays for the same circuit implemented in FPGAs with different speed grades.