Static random access memory cell having a thin film transistor (TFT) pass gate connection to a bit line

• US 5,949,706 A
• Filed: 01/26/1999
• Issued: 09/07/1999
• Est. Priority Date: 03/01/1993
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Cooper, Kent J., Kuo, Clinton C. K., Chang, Ko-Min, Morton, Bruce L., Witek, Keith E.
• Primary Examiner(s): Mai, Son
• Application Number:
  US09/236,914
• Time in Patent Office: 224 Days
• Field of Search: 365/154, 365/156, 365/149, 365/190, 257/903, 257/904, 257/369, 257/372
• US Class Current: 365/156
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

Claims

1. A static random access memory cell comprising:

a voltage terminal;

means for storing a binary value coupled to the voltage terminal comprising two cross-coupled inverters;

a select gate having a first terminal coupled to the means for storing and a second terminal, wherein the select gate is further characterized as being a transmission gate which comprises at least one thin film transistor (TFT) overlying another transistor; and

a conductor coupled to the second terminal of the select gate to bit line detection circuitry.

2. A static random access memory (SRAM) device comprising:

a storage device having at least one pull up transistor coupled between a first power supply terminal and a storage node and a pull down transistor coupled between a second power supply terminal and the storage node; and

a pass device coupled between the storage node and a bit line conductor, the pass device having a first transistor formed in a substrate and coupled between the storage node and the bit line conductor and a second transistor overlying the first transistor and coupled between the storage node and the bit line conductor.

3. The static random access memory (SRAM) device of claim 2 wherein the at least one pull up transistor is at least one P channel transistor and the at least one pull down transistor is a N channel transistor.

4. The static random access memory (SRAM) device of claim 3 wherein the second transistor is a P channel thin film transistor (TFT) transistor overlying the first transistor which is an N channel transistor.

5. The static random access memory (SRAM) device of claim 2 wherein the first power supply terminal is a voltage grater than ground and the second voltage supply terminal is a ground terminal.

6. The static random access memory (SRAM) device of claim 2 wherein the substrate is a semiconductor on insulator (SOI) substrate.

7. The static random access memory (SRAM) device of claim 2 wherein static random access memory (SRAM) device is isolated from other static random access memory (SRAM) devices across the substrate via trench isolation regions.

8. The static random access memory (SRAM) device of claim 2 wherein pull up transistor is a thin film transistor (TFT) overlying the substrate.

9. The static random access memory (SRAM) device of claim 2 wherein first and second transistor are separated by a nitride layer formed over the first transistor.

10. The static random access memory (SRAM) device of claim 9 wherein first and second transistor are also separated by an oxide layer formed over the first transistor.

11. The static random access memory (SRAM) device of claim 9 wherein second transistor is an overgated thin film transistor (TFT) having a silicon-containing channel region.

12. A static random access memory (SRAM) device comprising:

a first inverter having a first P channel pull up transistor coupled between a power supply terminal and a first storage node and a first N channel pull down transistor coupled between the first storage node and a ground supply terminal, a gate electrode of the first P channel pull up transistor being coupled to a gate electrode of the first N channel pull down transistor to form a first interconnected gate structure;

a second inverter having a second P channel pull up transistor coupled between the power supply terminal and a second storage node and a second N channel pull down transistor coupled between the second storage node and the ground supply terminal, a gate electrode of the second P channel pull up transistor being coupled to a gate electrode of the second N channel pull down transistor to form a second interconnected gate structure;

a first conductive portion coupling the first interconnected gate structure to the second storage node and a second conductive portion coupling the second interconnected gate structure to the first storage node; and

a thin film transistor overlying a substrate and coupled between the first storage node and a bit line conductor.

13. The static random access memory (SRAM) device of claim 12 wherein a pass transistor is underlying the thin film transistor and is coupled between the bit line conductor and the first storage node.

14. The static random access memory (SRAM) device of claim 13 wherein the pass transistor is an N channel transistor and the thin film transistor is a P channel transistor.

15. The static random access memory (SRAM) device of claim 13 wherein the pass transistor and the thin film transistor are separated by a nitride layer.

16. The static random access memory (SRAM) device of claim 12 wherein the first and second P channel pull up transistors are thin film transistors that overly the substrate.

17. The static random access memory (SRAM) device of claim 12 wherein the substrate is a silicon in insulator (SOI) substrate.

18. The static random access memory (SRAM) device of claim 12 wherein the static random access memory (SRAM) device is isolated by a trench isolation region.

19. The static random access memory (SRAM) device of claim 12 wherein the thin film transistor overlies a oxide-nitride-oxide (ONO) layer.

20. The static random access memory (SRAM) device of claim 12 wherein the thin film transistor is subject to a recrystallization operation to further crystallize a material used to form a channel region of the thin film transistor.

21. A static random access memory (SRAM) device comprising:

a first inverter having a first P channel TFT pull up transistor coupled between a power supply terminal and a first storage node and a first N channel pull down transistor coupled between the first storage node and a ground supply terminal, a gate electrode of the first P channel TFT pull up transistor being coupled to a gate electrode of the first N channel pull down transistor to form a first interconnected gate structure;

a second inverter having a second P channel TFT pull up transistor coupled between the power supply terminal and a second storage node and a second N channel pull down transistor coupled between the second storage node and the ground supply terminal, a gate electrode of the second P channel TFT pull up transistor being coupled to a gate electrode of the second N channel pull down transistor to form a second interconnected gate structure;

a first conductive portion coupling the first interconnected gate structure to the second storage node and a second conductive portion coupling the second interconnected gate structure to the first storage node;

a pass device having an N channel pass transistor formed in a silicon on insulator substrate and a P channel thin film transistor formed over the N channel pass transistor, the N channel pass transistor being separated from the P channel thin film transistor by a dielectric layer, the N channel pass transistor and the P channel thin film transistor each being coupled between the first storage node and a bit line conductor; and

a trench isolation region adjacent the static random access memory (SRAM) device.