Electrically programmable memory, method of programming and method of reading

• US 5,949,709 A
• Filed: 06/23/1998
• Issued: 09/07/1999
• Est. Priority Date: 08/31/1995
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Birnie, Andrew
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US09/029,598
• Time in Patent Office: 441 Days
• Field of Search: 365/185.03, 365/185.21, 365/185.19, 365/185.18
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits

Abstract

An electrically programmable memory comprising: a floating gate FET cell (10) having: a drain electrode, and a source electrode; means for applying to the drain electrode a first voltage (V_PP) for a programming time (T_P); means for applying to the source electrode a second voltage (V_ML) for the programming time, the second voltage being variable between more than two levels so as to determine the quantity of charge induced on the floating gate and thereby to determine the multi-level value programmed into the cell substantially independently of the programming time. A multi-level value programmed into the cell is sensed by placing an iteratively or dynamically varying voltage on the source electrode, and current flow in the cell is sensed to determine the voltage on the floating gate.

Claims

1. An electrically programmable memory comprising:

a floating gate FET cell having;

a drain electrode, and

a source electrode;

means for applying to one of the drain and source electrodes a first relatively high voltage for a programming time;

means for applying to the other of the drain and source electrodes a second voltage less than the first voltage for the programming time, the second voltage being variable between more than two levels so as to determine the quantity of charge induced on the floating gate FET cell and thereby to determine a multi-level value programmed into the cell substantially independently of the programming time.

2. An electrically programmable memory as claimed in claim 1 further comprising a thin insulating layer arranged between the floating gate and the remainder of the FET.

3. An electrically programmable memory as claimed in claim 1 wherein the floating gate comprises a polysilicon material.

4. An electrically programmable memory as claimed in claim 1 wherein the one of the drain and source electrodes is a drain electrode.

5. An electrically programmable memory as claimed in claim 1 wherein the other of the drain and source electrodes is a source electrode.

6. An electrically programmable memory as claimed in any preceding claim wherein the memory is an electrically e rasable read-only memory (E² PROM).

7. A method of programming an electrically programmable memory comprising:

a floating gate FET cell having;

a drain electrode, and

a source electrode;

the method comprising;

applying to one of the drain and source electrodes a first relatively high voltage for a programming time; and

applying to the other of the drain and source electrodes a second voltage less than the first voltage for the programming time, the second voltage being variable between more than two levels so as to determine the quantity of charge induced on the floating gate FET cell and thereby to determine a multi-level value programmed into the cell substantially independently of the programming time.

8. A method of reading an electrically programmed memory comprising:

a floating gate FET cell having;

a drain electrode; and

a source electrode,

the method comprising;

applying to one of the drain and source electrodes a third voltage; and

applying to the other of the drain and source electrodes a fourth, varying voltage, less than the third voltage; and

sensing current flow in the cell so as to determine a multi-level value programmed into the cell.

9. The method of claim 8 wherein the step of applying the fourth, varying voltage comprises applying a ramping voltage until current flow greater than a predetermined threshold occurs in the cell.

10. The method of claim 8 wherein the step of applying the fourth, varying voltage comprises applying a voltage having multiple levels in sequence and sensing whether current flow in the cell at each sequential level is greater than a predetermined threshold until the multi-level value programmed into the cell can be determined.