Data communication system and radio IC card system

• US 5,949,823 A
• Filed: 09/12/1997
• Issued: 09/07/1999
• Est. Priority Date: 09/13/1996
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nagai, Kenji, Suga, Takashi, Hayashi, Yoshihiko, Yoshino, Ryouzou
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): Tran, Congvan
• Application Number:
  US08/928,434
• Time in Patent Office: 725 Days
• Field of Search: 375/256, 375/219, 375/269, 375/272, 375/279, 375/316, 375/324, 375/340, 375/350, 375/376, 375/373, 329/304, 329/306, 329/309, 329/345, 329/346, 235/380
• US Class Current: 375/256
• CPC Class Codes: H04L 27/2271 wherein the carrier recovery circuit uses only the demodulated signals

Abstract

An arrangement to realize the functions of a radio card system in which power is transmitted to perform data communication. According to such arrangement, a delay line and a clock regenerating circuit such as PLL circuit which are previously necessary for demodulation by PSK are not necessary, and thus functions of data communication are realized by minimum hardware construction, size, cost and power consumption. Further, in a data communication system in which electric power transmission using a signal of a frequency fp and digital data communication using a carrier wave of a frequency fs are performed by radio, fs and fp are in the relationship of fs=fp/N (where N is an integer) and a phase shift P when the phase of the carrier wave is modulated by PSK is (M×360°)/N (where M, N are integers and P is preferably not equal to 180°).

Claims

1. An IC card comprising:

a receiver for receiving a modulated data signal transmitted from a base unit; and

a demodulator for demodulating the received modulated data signal, the demodulator effecting demodulation of the received modulated data signal exclusive of a phase-locked-loop (PLL) circuit;

wherein said demodulator comprises;

a plurality of phase comparator circuits, each phase comparator circuit comparing a phase of the received modulated data signal with a different reference phase, for substantial correspondence therebetween; and

a phase monitoring circuit monitoring phase comparison outputs from said plurality of phase comparator circuits, for detecting phase shifts in the received modulated data signal over time so as to demodulate the received modulated data signal,

wherein each said phase comparator circuit comprises an AND gate connected to receive the received modulated data signal at a first input thereof and the reference phase at a second input thereof.

2. An IC card according to claim 1, wherein each said phase comparator circuit further comprises a filter circuit.

3. An IC card according to claim 2, wherein said phase monitoring circuit is more specifically a microprocessor.

4. An IC card further comprising:

a receiver for receiving a modulated data signal transmitted from a base unit; and

a demodulator for demodulating the received modulated data signal, the demodulator effecting demodulation of the received modulated data signal exclusive of a phase-locked-loop (PLL) circuit;

a divide circuit for dividing a received power signal of a frequency fp so as to form a plurality of different reference phases of a frequency fs for use with said plurality of phase comparator circuits, wherein fs and fp are in a relationship of fs=fp/N (where N is an integer); and

wherein a phase shift P when a phase of the modulated data signal is modulated by PSK is (M×

360°

)/N (where M is an integer).

5. An IC card according to claim 4, wherein said phase shift P is not equal to 180°

.

6. An IC card comprising:

a receiver for receiving a modulated data signal transmitted from a base unit; and

a demodulator for demodulating the received modulated data signal, the demodulator effecting demodulation of the received modulated data signal exclusive of a phase-locked-loop (PLL) circuit;

wherein said demodulator comprises;

a divide circuit for dividing a received power signal of a frequency fp so as to form four different reference phases of a frequency fs for use with said plurality of phase comparator circuits, wherein fs and fp are in a relationship of fs=fp/4;

four phase comparator circuits, each phase comparator circuit including an AND gate comparing a phase of the received modulated data signal with a different reference phase from said divide circuit, for substantial correspondence therebetween; and

a phase monitoring microprocessor monitoring phase comparison outputs from said phase comparator circuits, for detecting phase shifts in the received modulated data signal from a current said phase comparator circuit to a different phase comparator circuit over time so as to demodulate the received modulated data signal.

7. A data communication system comprising:

a base unit for transmitting a modulated data signal; and

a mobile unit for receiving and demodulating the modulated data signal, the mobile unit including a demodulating circuit exclusive of a phase-locked-loop (PLL) circuit for demodulating the modulated data signal,

wherein said demodulating circuit comprises;

a plurality of phase comparator circuits, each phase comparator circuit comparing a phase of the received modulated data signal with a different reference phase, for substantial correspondence therebetween; and

a phase monitoring circuit monitoring phase comparison outputs from said plurality of phase comparator circuits, for detecting phase shifts in the received modulated data signal over time so as to demodulate the received modulated data signal,

wherein each said phase comparator circuit comprises an AND gate connected to receive the received modulated data signal at a first input thereof and the reference phase at a second input thereof.

8. A data communication system according to claim 7, wherein each said phase comparator circuit further comprises a filter circuit.

9. A data communication system according to claim 7, wherein said phase monitoring circuit is more specifically a microprocessor.

10. A data communication system further comprising:

a divide circuit for dividing a received power signal of a frequency fp so as to form a plurality of different reference phases of a frequency fs for use with said plurality of phase comparator circuits, wherein fs and fp are in a relationship of fs=fp/N (where N is an integer); and

wherein a phase shift P when a phase of the modulated data signal is modulated by PSK is (M×

360°

)/N (where M is an integer),

a divide circuit for dividing a received power signal of a frequency fp so as to form a plurality of different reference phases of a frequency fs for use with said plurality of phase comparator circuits, wherein fs and fp are in a relationship of fs=fp/N (where N is an integer); and

wherein a phase shift P when a phase of the modulated data signal is modulated by PSK is (M×

360°

), N (where M is an integer).

11. A data communication system according to claim 10, wherein said phase shift P is not equal to 180°

.

13. A data communication system according to claim 10, wherein the mobile unit is an IC card.

12. A data communication system comprises:

a divide circuit for dividing a received power signal of a frequency fp so as to form a plurality of different reference phases of a frequency fs for use with said plurality of phase comparator circuits, wherein fs and fp are in a relationship of fs=fp/N (where N is an integer); and

wherein a phase shift P when a phase of the modulated data signal is modulated by PSK is (M×

360°

)/N (where M is an integer),

a divide circuit for dividing a received power signal of a frequency fp so as to form four different reference phases of a frequency fs for use with said plurality of phase comparator circuits, wherein fs and fp are in a relationship of fs=fp/4;

four phase comparator circuits, each phase comparator circuit including an AND gate comparing a phase of the received modulated data signal with a different reference phase from said divide circuit, for substantial correspondence therebetween; and

a phase monitoring microprocessor monitoring phase comparison outputs from said phase comparator circuits, for detecting phase shifts in the received modulated data signal from a current said phase comparator circuit to a different phase comparator circuit over time so as to demodulate the received modulated data signal.

14. A data communication system

in which electric power transmission using a power signal of a frequency fp and digital data communication of a modulated data signal using a carrier wave of a frequency fs are performed by radio transmission from a base unit to a mobile unit, wherein fs and fp are in the relationship of fs=fp/N (where N is an integer) and a phase shift P when the phase of the carrier wave is modulated by PSK is (M×

360°

)/N (where M, N are integers and P is not equal to 180°

); and

comprising;

a divide circuit for dividing the power signal at the frequency fp so as to form synchronization signals of a plurality of different phases at said frequency fs for enabling demodulation of the modulated data signal; and

a demodulator utilizing said plurality of different phases for demodulating the received modulated data signal, the demodulator effecting demodulation of the received modulated data signal exclusive of a phase-locked-loop (PLL) circuit.