Continuous integration digital demodulator for use in a communication device

• US 5,949,827 A
• Filed: 09/19/1997
• Issued: 09/07/1999
• Est. Priority Date: 09/19/1997
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: DeLuca, Michael J., Quiroga, Emilio J.
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Bayard, Emmanuel
• Application Number:
  US08/934,404
• Time in Patent Office: 718 Days
• Field of Search: 375/316, 375/322, 375/324, 375/340, 329/315, 329/321, 329/323, 455/205, 455/208, 455/210, 455/255, 455/67.3, 455/63, 455/501, 365/724.1
• US Class Current: 375/324
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A digital demodulator (100) for use in a communication device comprising a mixer (110) which samples a limited IF signal derived from a received radio frequency (RF) signal at a rate less than a Nyquist rate of the limited IF signal and generates a resulting IF signal. A continuous integrator (130) is connected to the mixer (110) and integrates the resulting IF signal over a predetermined number of samples thereof to generate a numerical value representative of a modulation frequency of a limited IF signal. An adaptive peak-valley bit slicer (150) is connected to the continuous integrator (130) and compares each numerical value with a peak threshold, a valley threshold and a mid threshold and generates most-significant-bit (MSB) and least-significant-bit (LSB) values for each sample. The adaptive peak-valley bit slicer (150) adjusts the peak and valley thresholds for use in determining a level of a current numerical value based on the LSB and MSB values determined for a prior sample of the numerical value.

Claims

1. A digital demodulator comprising:

an oscillator generating as output an oscillator clock signal;

a frequency divider coupled to the oscillator clock signal, wherein the oscillator generates the oscillator clock signal at a first frequency and the frequency divider divides the oscillator clock signal by a divider factor to generate a sampling clock signal at a second;

a mixer coupled to the sampling clock signal, the mixer suitable for receiving as input a limited IF signal derived from a received radio frequency (RF) signal and sampling the limited IF signal in accordance with the sampling clock signal to generate as output a resulting IF signal;

a continuous integrator connected to the mixer and coupled to the sampling clock signal, the continuous integrator integrating the resulting IF signal over a predetermined number of samples of the limited IF signal to generate a numerical value representative of a modulation frequency of a baseband signal, the continuous integrator being driven by the sampling clock signal and generating as output a numerical value for each sample of the limited IF signal; and

a peak-valley bit slicer connected to the continuous integrator and to the oscillator, the peak-valley bit slicer comparing each numerical value with thresholds to determine corresponding digital data of the baseband signal.

2. The digital demodulator of claim 1, wherein the mixer samples the limited IF signal at a sampling rate which is less than a Nyquist sampling rate of a frequency band to which the limited IF signal is band-limited.

3. The digital demodulator of claim 1, wherein the mixer comprises:

a flip-flop having a data input connected to receive the limited IF signal, a data output, and a clock input coupled to the frequency divider for receiving the sampling clock signal;

an exclusive-OR gate having first and second inputs and an output, the first input connected to receive the limited IF signal and the second input connected to the data output of the flip-flop, the exclusive-OR gate generating a pulse on its output in response to detecting a difference between a level of the limited IF signal at successive cycles of the sampling clock signal.

4. The digital demodulator of claim 1, wherein the frequency divider divides the oscillator clock signal by a divider factor depending on an expected baud rate of the digital data in the baseband signal.

5. The digital demodulator of claim 1, wherein the continuous integrator comprises:

a shift register having a plurality of bit positions;

a first counter connected to the shift register for counting weighted values for each position of the shift register to generate a count value for each sample, the weighted values being assigned depending on a relative position in the shift register and a bit value at each position;

a circular buffer comprising a plurality of accumulators each storing a count value for prior symbol samples; and

a second counter connected to the accumulators for adding count values stored in all of the accumulators and generating a preliminary numerical value.

6. The digital demodulator of claim 5, wherein the continuous integrator further comprises:

a multiplier connected to the second counter for multiplying the preliminary numerical value by a multiplier factor depending on an expected baud rate of the digital data in the baseband signal to generate the numerical value.

7. The digital demodulator of claim 5, wherein the first counter assigns a greater weighted value for transitions occurring at a center of a symbol integration time period than for transitions occurring at a beginning or an end of the symbol integration time period.

8. The digital demodulator of claim 5, wherein the predetermined number of samples is 50, a number of bits in the shift register is 40 and a number of accumulators in the circular buffer is 10, and wherein the first counter assigns a weighted value of "one" to transitions occurring in first two and last two bit positions of the shift register, a weighted value of "two" to transitions occurring in second two and second to last two bit positions, and a weighted value of "three" to transitions occurring in any of thirty two bit positions in a center of the shift register.

9. The digital demodulator of claim 1, wherein the peak-valley bit slicer compares the numerical value output by the continuous integrator with a peak threshold, a valley threshold and a mid threshold and generates digital data for each sample.

10. The digital demodulator of claim 9, wherein the peak-valley bit slicer adjusts the peak and valley thresholds for use in determining a level of a current sample of the numerical value based on the digital data determined for a prior sample.

11. The digital demodulator of claim 1, wherein the peak-valley bit slicer adjusts the thresholds for use in determining the digital data for a current sample of the numerical value based on digital data determined for a prior sample of the numerical value.

12. The digital demodulator of claim 11, wherein the peak-valley bit slicer adjusts the peak and valley thresholds when the digital data determined for a prior sample corresponds to outer levels of a 4-level FM signal.

13. The digital demodulator of claim 1, wherein the peak-valley bit slicer comprises:

a peak detector receiving as input the numerical value generated by the continuous integrator and comparing a current sample of the numerical value with a prior sample thereof to provide as output a current peak value;

a valley detector receiving as input the numerical value generated by the continuous integrator and comparing a current sample of the numerical value with a prior sample thereof to provide as output a current valley value;

an arithmetic logic circuit connected to the peak detector and to the valley detector to receive as input the current peak value and the current valley value, the arithmetic logic circuit generating as output first and second peak thresholds, a mid threshold and first and second valley thresholds based on the current peak value and the current valley value;

a first selector switch connected to the arithmetic logic circuit and receiving the first and second peak thresholds, the first selector switch supplying as output either the first peak threshold or the second peak threshold;

a second selector switch connected to the arithmetic logic circuit and receiving the first and second valley thresholds, the second selector switch supplying as output either the first valley threshold or the second valley threshold;

a level comparator connected to the arithmetic logic circuit and to the output of the first and second selector switches, the level comparator comparing the numerical value with one of the first and second peak thresholds, the mid threshold and one of the first and second valley thresholds, to generate as output least-significant-bit (LSB) and most-significant-bit (MSB) values depending on a level of the numerical value; and

a transition comparator receiving as input LSB and MSB values for a prior sample of the numerical value and controlling which of the first and second peak thresholds the first selector switch supplies as output and which of the first and second valley thresholds the second selector switch supplies as output.

14. The digital demodulator of claim 13, wherein the arithmetic logic circuit generates the first and second peak thresholds such that the first peak threshold is greater than the second peak threshold, and generates the first and second valley thresholds such that the second valley threshold is less than the first valley threshold.

15. The digital demodulator of claim 14, wherein the transition comparator controls the first selector switch to supply as output the second peak threshold when the LSB and MSB values for a prior sample are both "0" and otherwise controls the first selector switch to supply as output the first peak threshold, and controls the second selector switch to supply as output the second valley threshold when the LSB and MSB values for a prior sample are "1" and "0", respectively, and otherwise controls the second selector switch to supply as output the first valley threshold.

16. An RF communication device comprising the digital demodulator of claim 1.

17. In combination on a single integrated circuit, the digital demodulator of claim 1 and a decoder coupled to the digital demodulator to receive and decode the digital data output by the digital demodulator.

18. The combination of claim 17, wherein the decoder controls a frequency of a sampling clock signal for the mixer and continuous integrator based upon an expected baud rate of the digital data in the baseband signal.

19. The combination of claim 17, wherein the continuous integrator comprises:

a shift register having a plurality of bit positions;

a first counter connected to the shift register for counting weighted values for each position of the shift register to generate a count value for each sample, the weighted values being assigned depending on a relative position in the shift register and a bit value at each position;

a circular buffer comprising a plurality of accumulators each storing a count value for prior symbol samples; and

a second counter connected to the accumulators for adding count values stored in all of the accumulators and generating a preliminary numerical value; and

a multiplier connected to the second counter for multiplying the preliminary numerical value by a multiplier factor to generate the numerical value representing the modulation frequency of the baseband signal; and

wherein the decoder controls the divider factor of the frequency divider and the multiplier factor of the multiplier according to an expected baud rate of the digital data in the baseband signal.

20. A selective call receiver comprising the digital demodulator of claim 1, wherein the selective call receiver comprises:

a receiver for receiving an RF signal and generating as output the limited IF signal;

a decoder coupled to the peak-valley bit slicer to receive and decode the digital information; and

a controller coupled to the decoder and to the receiver for processing the digital information decoded by the decoder.

21. A digital demodulator for use in a receiver comprising:

an oscillator generating as output an oscillator clock signal;

a frequency divider coupled to the oscillator and receiving as input the oscillator clock signal and frequency dividing the oscillator clock signal by a divider factor to generate as output a sampling clock signal;

a mixer coupled to the sampling clock signal, the mixer suitable for receiving as input a limited IF signal derived from a received radio frequency (RF) signal and sampling the limited IF signal in accordance with the sampling clock signal derived from the oscillator clock signal to generate as output a resulting IF signal;

a continuous integrator connected to the mixer and coupled to the sampling clock signal, the continuous integrator integrating the resulting IF signal over a predetermined number of samples of the limited IF signal to generate a numerical value representative of a modulation frequency of a baseband signal, the continuous integrator being driven by the sampling clock signal and generating as output a numerical value for each sample of the limited IF signal;

an adaptive peak-valley bit slicer connected to the continuous integrator and to the sampling clock signal, the adaptive peak-valley bit slicer comparing each numerical value with a peak threshold, a valley threshold and a mid threshold and generating digital data comprising most-significant-bit (MSB) and least-significant-bit (LSB) values for each sample, wherein the adaptive peak-valley bit slicer adjusts the peak and valley thresholds for use in determining a level of a current sample of the numerical value based on the LSB and MSB values determined for a prior sample.

22. The digital demodulator of claim 21, wherein the adaptive peak-valley bit slicer adjusts the peak and valley thresholds when the LSB and MSB values determined for a prior sample correspond to outer levels of a 4-level FM signal.

23. The digital demodulator of claim 21, wherein the adaptive peak-valley bit slicer comprises:

a peak detector receiving as input the numerical value generated by the continuous integrator and comparing a current sample of the numerical value with a prior sample thereof to provide as output a current peak value;

a valley detector receiving as input the numerical value generated by the continuous integrator and comparing a current sample of the numerical value with a prior sample thereof to provide as output a current valley value;

an arithmetic logic circuit connected to the peak detector and to the valley detector to receive as input the current peak value and the current valley value, the arithmetic logic circuit generating as output first and second peak thresholds, a mid threshold and first and second valley thresholds based on the current peak value and the current valley value;

a first selector switch connected to the arithmetic logic circuit and receiving the first and second peak thresholds, the first selector switch supplying as output either the first peak threshold or the second peak threshold;

a second selector switch connected to the arithmetic logic circuit and receiving the first and second valley thresholds, the second selector switch supplying as output either the first valley threshold or the second valley threshold;

a level comparator connected to the arithmetic logic circuit and to the output of the first and second selector switches, the level comparator comparing the numerical value with one of the first and second peak thresholds, the mid threshold and one of the first and second valley thresholds, to generate as output least-significant-bit (LSB) and most-significant-bit (MSB) values depending on a level of the numerical value relative to the thresholds; and

a transition comparator receiving as input LSB and MSB values for a prior sample of the numerical value and controlling which of the first and second peak thresholds the first selector switch supplies as output and which of the first and second valley thresholds the second selector switch supplies as output.

24. The digital demodulator of claim 23, wherein the arithmetic logic circuit generates the first and second peak thresholds such that the first peak threshold is greater than the second peak threshold, and generates the first and second valley thresholds such that the second valley threshold is less than the first valley threshold.

25. The digital demodulator of claim 24, wherein the transition comparator controls the first selector switch to supply as output the second peak threshold when the LSB and MSB values for a prior sample are both "0" and otherwise controls the first selector switch to supply as output the first peak threshold, and controls the second selector switch to supply as output the second valley threshold when the LSB and MSB values for a prior sample are "1" and "0", respectively, and otherwise controls the second selector switch to supply as output the first valley threshold.

26. In combination on a single integrated circuit, the digital demodulator of claim 21, and a decoder coupled to the digital demodulator to receive and decode the digital data output by the digital demodulator.

27. The combination of claim 26, wherein the decoder controls a frequency of the sampling clock signal for the mixer and continuous integrator based upon an expected baud rate of digital data in the baseband signal.

28. A selective call receiver comprising the digital demodulator of claim 21, wherein the selective call receiver comprises:

a receiver for receiving an RF signal and generating as output the limited IF signal;

a decoder coupled to the peak-valley bit slicer to receive and decode the digital information; and

a controller coupled to the decoder and to the receiver for processing the digital information decoded by the decoder.

29. In combination, a digital demodulator and control means for controlling the digital demodulator, the digital demodulator comprising:

an oscillator generating as output an oscillator clock signal;

a frequency divider connected to the oscillator and receiving as input the oscillator clock signal and frequency dividing the oscillator clock signal by a divider factor to generate as output a sampling clock signal;

a mixer connected to the frequency divider, the mixer suitable for receiving as input a limited IF signal derived from a received radio frequency (RF) signal and sampling the limited IF signal in accordance with the sampling clock signal to generate as output a resulting IF signal;

a continuous integrator connected to the frequency divider and coupled to the oscillator, the continuous integrator integrating the resulting IF signal over a predetermined number of samples of the limited IF signal, the continuous integrator being driven by the sampling clock signal and generating a preliminary numerical value for each sample of the limited IF signal, the continuous integrator comprising a multiplier for multiplying the preliminary numerical value by a multiplier factor in order to generate a numerical value representative of a modulation frequency of a baseband signal; and

a peak-valley bit slicer connected to the continuous integrator and to the oscillator, the peak-valley bit slicer comparing each numerical value with thresholds to determine corresponding digital data of the baseband signal;

wherein the control means controls the divider factor of the frequency divider and the multiplier factor of the multiplier depending upon an expected baud rate of the digital data in the baseband signal.