Apparatus and method for cryptographic companion imprinting

• US 5,949,881 A
• Filed: 12/04/1995
• Issued: 09/07/1999
• Est. Priority Date: 12/04/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Davis, Derek L.
• Primary Examiner(s): Buczinski, Stephen C.
• Application Number:
  US08/566,910
• Time in Patent Office: 1,373 Days
• Field of Search: 380/23, 380/25, 380/49
• US Class Current: 713/189
• CPC Class Codes: G06F 21/34 involving the use of external additional devices, e.g. dongles or smart cards
• CPC Class Codes: G06F 21/445 by mutual authentication, e.g. between devices or programs
• CPC Class Codes: G06F 2211/009 Trust

Abstract

A mechanism to conditionally activate an electronic device implemented within electronic computing equipment such as a computer. Such activation may be based on user authentication and/or confirmation that the electronic device is operating in conjunction with its companion cryptographic device.

Claims

1. A node comprising:

a system processor including;

a semiconductor package,

a processor core contained in the semiconductor package and initially placed in a non-functional state, and

an empowerment unit contained in the semiconductor package and coupled to the processor core, the empowerment unit placing the processor core into a functional state where the processor core is operative upon receiving an encrypted, authorization message; and

a cryptographic device coupled to the empowerment unit of the system processor, the cryptographic device including a processing unit transmitting the authorization message to the empowerment unit in order to place the processor core in the functional state after confirming that the cryptographic device is in communication with the system processor.

2. The node according to claim 1, wherein the processor core of the system processor is placed in the functional state by deactivating a reset signal provided to the system processor, the reset signal continuously being active while the system processor is in the non-functional state.

3. The node according to claim 2, wherein the cryptographic device includes a coprocessor.

4. The node according to claim 1, wherein the cryptographic device places the processor core of the system processor in the functional state by signaling the empowerment unit to allow power to be supplied to the processor core.

5. The node according to claim 1, wherein the system processor includes a random number generator to generate a temporary session key to be used between the cryptographic device and the system processor after verification that the cryptographic device is in communication with the empowerment unit of the system processor.

6. A node requiring authentication of its user to be functional, the node comprising:

a bus; and

a system processor coupled to the bus, the system processor including

a semiconductor package,

a processor core contained in the semiconductor package, the processor core being initially placed in a non-functional state, and

a cryptographic processing unit coupled to at least the processor core and contained in the semiconductor package, the cryptographic processing unit placing the processor core in a functional state upon establishing that the cryptographic processing unit is in communication with the processor core.

7. The node of claim 6, wherein in the non-functional state, the processor core is maintained in a reset state.

8. A method for conditionally activating an integrated circuit device implemented in a node along with a companion device, the method comprising:

powering up the node;

disabling the integrated circuit device at power up of the node to prevent the integrated circuit device from processing digital information, the integrated circuit device permanently containing a device identification;

verifying that a user of the node is authorized to use the node;

confirming that the integrated circuit device is operating in conjunction with the companion device, the companion device permanently containing the device identification; and

enabling the integrated circuit device if the user is verified and the integrated circuit device is confirmed to be operating in conjunction with the companion device.

9. The method according to claim 8, wherein the confirming that the integrated circuit is operating in conjunction with the companion device includes

encrypting a challenge using the device identification contained in the companion device;

transmitting the encrypted challenge to the integrated circuit device;

receiving the encrypted challenge by the integrated circuit device;

decrypting the encrypted challenge with the device identification contained in the integrated circuit device;

encrypting a response to the challenge using the device identification contained in the integrated circuit device;

transmitting the encrypted response from the integrated circuit device to the companion device; and

decrypting the response thereby determining that the integrated circuit device and the companion device are operating in conjunction with each other.

10. The method according to claim 9, wherein the response produced by the integrated circuit device includes contents of the challenge produced by the companion device and a random bit string.

11. A computer comprising:

a system processor including;

a semiconductor package,

a processor core contained in the semiconductor package, and

an empowerment unit contained in the semiconductor package and coupled to the processor core, the empowerment unit controlling an operating state of the processor core by (i) placing the processor core in a non-functional state in response to a first event so that the processor core is inoperative, and alternatively (ii) placing the processor core in a functional state in response to a second event; and

a cryptographic device coupled to the system processor, the cryptographic device signaling the empowerment unit to place the processor core in the functional state.

12. The computer according to claim 11, wherein the first event includes initial power-up of the computer.

13. The computer according to claim 12, wherein the second event includes confirmation that the cryptographic device is in communication with the system processor.

14. The computer according to claim 13, wherein the second event further includes authentication of a user of the computer.

15. The computer according to claim 11, wherein the cryptographic device signals the empowerment unit to discontinue providing NO OPERATION instructions for execution by the system processor so as to control the operating state of the system processor.

16. The computer according to claim 11, wherein the cryptographic device signals the empowerment unit to allow power to be supplied to the processor core of the system processor so as to control the operating state of the system processor.

17. The computer according to claim 11, wherein the cryptographic device signals the empowerment unit to deactivate a reset signal supplied to the processor core of the system processor so as to control the operating state of the system processor.

18. A computer comprising:

a semiconductor device package;

processing means contained in the semiconductor device package for processing digital information, the processing means being initially placed in a non-functional state after power is applied thereto; and

cryptographic means for placing the processing means in a functional state after verifying that the cryptographic means is in communication with the processor means, the cryptographic means being contained in the semiconductor device package.