Apparatus and method for shutdown of wireless communications mobile station with multiple clocks

• US 5,950,120 A
• Filed: 06/17/1997
• Issued: 09/07/1999
• Est. Priority Date: 06/17/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Young, Linley M., White, Peter P., Gardner, William R.
• Primary Examiner(s): Bost, Dwayne D.
• Assistant Examiner(s): LEGREE, TRACY MICHELLE
• Application Number:
  US08/877,215
• Time in Patent Office: 812 Days
• Field of Search: 455/343, 455/574, 455/115, 455/403, 455/110, 455/116, 455/109, 455/38.3, 375/316, 375/376
• US Class Current: 455/343.1
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: H04W 52/0293 having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

The present invention presents a mobile station of a wireless communications system such that when the mobile station is in idle mode (i.e., listening to a paging channel periodically, but otherwise taking no action), the control processor commands the mobile station to enter into sleep mode to minimize power consumption. During sleep mode, the high-frequency reference clock and thus all high-frequency clocks derived from it are turned off. Only a low-frequency clock remains operating at all times to clock the sleep logic.

Claims

1. A wireless communications mobile station comprising:

a. radio frequency circuitry for receiving and modulating radio signals;

b. first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals;

c. baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals, wherein said baseband processing circuitry comprises a control processor and a digital signal processor and wherein the control processor is operationally connected to the first clock via a phase lock loop which up-converts the frequency of the reference signal from the first clock;

d. second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals;

e. a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry;

f. a first reference clock operationally connected to said baseband processing circuitry which provides an approximate 13 MHz reference signal;

g. a second clock which runs at a frequency lower than 13 Mhz; and

h. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a sleep mode in which said first clock is turned off and the second clock serves as a timing reference for the sleep logic circuitry.

2. A wireless communications mobile station comprising:

a. radio frequency circuitry for receiving and modulating radio signals;

b. first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals;

c. baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals, wherein said baseband processing circuitry comprises a control processor and a digital signal processor and wherein the digital signal processor is operationally connected to the first clock via a phase lock loop which up-converts the frequency of the reference signal from the first clock;

d. second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals;

e. a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry;

f. a first reference clock operationally connected to said baseband processing circuitry which provides an approximate 13 MHz reference signal;

g. a second clock which runs at a frequency lower than 13 Mhz; and

h. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a sleep mode in which said first clock is turned off and the second clock serves as a timing reference for the sleep logic circuitry.

3. Digital circuitry for a wireless communications mobile station comprising:

a. baseband processing circuitry for processing digitized radio signals, said baseband processing circuitry comprises a control processor and a digital signal processor wherein the control processor is operationally connected to the first clock via a phase lock loop which up-converts the frequency of the reference signal from the first clock;

b. a first reference clock operationally connected to said baseband processing circuitry and providing an approximate 13 MHz reference signal,

c. a second clock which runs at a frequency lower than 13 MHz; and

d. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a mode in which said first clock is shut down and the second clock serves as a timing reference for the sleep logic circuitry.

4. Digital circuitry for a wireless communications mobile station comprising:

a. baseband processing circuitry for processing digitized radio signals, said baseband processing circuitry comprises a control processor and a digital signal processor wherein the digital signal processor is operationally connected to the first clock via a phase lock loop which up-converts the frequency of the reference signal from the first clock;

b. a first reference clock operationally connected to said baseband processing circuitry and providing an approximate 13 MHz reference signal;

c. a second clock which runs at a frequency lower than 13 MHz; and

d. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a mode in which said first clock is shut down and the second clock serves as a timing reference for the sleep logic circuitry.

5. A wireless communications system comprising:

a. a mobile station,

b. a base station subsystem which controls the radio link with the mobile station, and

c. a network subsystem which is interfaced with a public fixed network and the base station subsystem, wherein said mobile station comprises the following;

i. radio frequency circuitry for receiving and modulating radio signals;

ii. first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals;

iii. baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals;

iv. second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals,

v. a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry;

vi. a first reference clock operationally connected to said baseband processing circuitry providing a first reference signal;

vii. a second clock which runs at a freguency lower than the frequency of the first clock wherein said second clock runs between 32 kHz minus 50 ppm and 32 kHz plus 50 ppm; and

viii. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a sleep mode in which said first clock is turned off and the second clock serves as a timing reference for the sleep logic circuitry,

ix. a calibrator to calibrate the signal of the second clock prior to sleep mode.