Method and apparatus for serialized interrupt transmission
First Claim
1. An interrupt handling apparatus comprising:
- a first I/O controller in a first packaged integrated circuit chip, said first I/O controller receives or generates a plurality of incoming interrupt signals from a plurality of devices;
an interrupt controller in a second packaged integrated circuit chip, said interrupt controller processes interrupts for a plurality of devices;
a serial data link operatively connecting said first I/O controller of the first packaged integrated circuit chip and said interrupt controller of the second packaged integrated circuit chip; and
a synchronization link operatively connecting said interrupt controller of the second packaged integrated circuit chip and said first I/O controller of the first packaged integrated circuit chip,wherein a synchronization signal is transmitted from said interrupt controller to said first I/O controller over said synchronization link, and the incoming interrupt signals are serially transmitted from said first I/O controller to said interrupt controller over said serial data link in accordance with the synchronization signal, andwherein the synchronization signal operates to align the serial transmission of the incoming interrupt signals with processing of the interrupts by said interrupt controller subject to a predetermined offset amount.
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Abstract
A computer system in which interrupt signals are serially transmitted from an input/output (I/O) controller is disclosed. The I/O controller initially receives the interrupt signals and then serially transmits them to an interrupt controller where the received interrupt signals are managed. According to the invention, the sequencing by which the interrupt signals are serially transmitted is controlled such that it largely conforms to the sequencing by which the received interrupt signals are processed at the interrupt controller, thereby controlling and reducing latency. The interrupt controller can be a separate integrated circuit chip or integral to another integrated circuit chip of the computer system.
37 Citations
22 Claims
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1. An interrupt handling apparatus comprising:
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a first I/O controller in a first packaged integrated circuit chip, said first I/O controller receives or generates a plurality of incoming interrupt signals from a plurality of devices; an interrupt controller in a second packaged integrated circuit chip, said interrupt controller processes interrupts for a plurality of devices; a serial data link operatively connecting said first I/O controller of the first packaged integrated circuit chip and said interrupt controller of the second packaged integrated circuit chip; and a synchronization link operatively connecting said interrupt controller of the second packaged integrated circuit chip and said first I/O controller of the first packaged integrated circuit chip, wherein a synchronization signal is transmitted from said interrupt controller to said first I/O controller over said synchronization link, and the incoming interrupt signals are serially transmitted from said first I/O controller to said interrupt controller over said serial data link in accordance with the synchronization signal, and wherein the synchronization signal operates to align the serial transmission of the incoming interrupt signals with processing of the interrupts by said interrupt controller subject to a predetermined offset amount. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An interrupt controller for receiving and processing a plurality of interrupt signals from a plurality of devices, said interrupt controller comprises:
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a serial data input port for receiving a serial stream of interrupt signals from an I/O controller; processing means for sequentially selecting and processing each of the interrupt signals within the serial stream; a synchronization manager for producing a synchronization signal, the synchronization signal being used to align the transmission of the interrupt signals within the serial stream to the respective processing of the received interrupt signals by said processing means; and a synchronization signal output port for forwarding the synchronization signal from said interrupt controller to the I/O controller. - View Dependent Claims (13, 14, 15)
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16. A method for synchronizing transmission of interrupt signals from a first integrated circuit chip that receives the interrupt signals to an interrupt controller, said method comprising:
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(a) placing the interupt signals to be transmitted in a first sequential order; (b) receiving an alignment signal from the interrupt controller, the alignment signal being received over a synchronization link provided from the interrupt controller to the first integrated circuit chip; and (c) serially transmitting the interrupt signals to the interrupt controller over a serial data link in accordance with the first sequential order and the alignment signal such that the transmission of the interrupt signals is aligned with processing of the interrupt signals at the interrupt controller so as to reduce latency. - View Dependent Claims (17)
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18. A method as recited in 16, wherein said method further comprises:
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(d) receiving the transmitted interrupt signals at the interrupt controller; (e) processing the received interrupt signals in a second sequential order; and (f) producing and transmitting the alignment signal based on the second sequential order.
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19. A method for transmitting interrupt signals to an interrupt controller from a first integrated circuit chip, said method comprising:
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(a) placing the interrupt signals to be transmitted in a first sequential order; (b) serially transmitting the interrupt signals to the interrupt controller over a serial data link in accordance with the first sequential order; (c) receiving the series transmission of the interrupt signals at the interrupt controller; (d) processing the received interrupt signals at the interrupt controller in a second sequential order; and (e) forwarding a synchronization signal from the interrupt controller to the first integrated circuit ship over a synchronization link to indicate a position in the second sequential order with respect to the first sequential order. - View Dependent Claims (20, 21, 22)
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Specification