Error correction coding and decoding method, and circuit using said method

• US 5,951,708 A
• Filed: 03/26/1998
• Issued: 09/14/1999
• Est. Priority Date: 05/30/1995
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yoshida, Hideo
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US09/048,954
• Time in Patent Office: 537 Days
• Field of Search: 714/752, 714/757, 714/763, 714/772, 714/773
• US Class Current: 714/752
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/151 using error location or error correction polynomials
• CPC Class Codes: H03M 13/47 Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37

Abstract

In the coding and decoding of Reed-Solomon codes formed of symbols larger than information symbols, redundant circuitry is eliminated, error detection and correction are preformed using a simple construction, and the reliability of error detection and correction is improved by processing only data of the same size as the information symbols. Two bits of dummy data which are surplus bits in 10 bits of one symbol of information are supplied from a dummy data input circuit to 8 bit input data. At the same time, syndrome data is generated form the surplus parts of check symbols by a syndrome data correction circuit. A part of the 10 bit data is selected by a selector, and supplied to a Galois field summation circuit. The output of the Galois field summation circuit is output to a register, and the output of this register is either selected without modification or via a Galois field coefficient multiplying circuit by a selector, and supplied to the Galois field summation circuit. The output of the register is output as syndrome data by a syndrome output terminal.

Claims

1. An error correction coding/decoding method wherein error correction coding and decoding comprises a process which treats the weighting of a parity check matrix only as "1", "3" or "7" in a (76, 64) binary linear code that performs 1 bit error correction and 2 bit error detection.

3. An error correction coding/decoding method as defined in claim 1 comprising a process which, in decoding a (76, 64) binary linear code, treats said parity check matrix as ##EQU3##

2. A decoding circuit used for decoding a (76, 64) binary linear code, said circuit comprising:

syndrome calculating means for performing syndrome calculation,

error correction means for performing error correction, and

error correction impossibility detecting means which determines that error correction is impossible when the bit weighting of an 8 bit syndrome is an even number excluding all "0", or 5.