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Topography monitor

  • US 5,952,674 A
  • Filed: 03/18/1998
  • Issued: 09/14/1999
  • Est. Priority Date: 03/18/1998
  • Status: Expired due to Fees
First Claim
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1. A topography monitor for an integrated circuit chip wafer comprising:

  • an area of topography,a conformal insulator layer applied over the area of topography, anda conductive layer fabricated as a pattern in the conformal insulator layer, where the pattern is intended by design to produce two or more runs of conductor in registration with the area of topography and in close proximity to each other,wherein a depression in the area of topography causes a resistance between two runs of conductor overlying the depression to be lower than a resistance between two runs of conductor when no defect is in the area of topography.

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