Topography monitor
First Claim
1. A topography monitor for an integrated circuit chip wafer comprising:
- an area of topography,a conformal insulator layer applied over the area of topography, anda conductive layer fabricated as a pattern in the conformal insulator layer, where the pattern is intended by design to produce two or more runs of conductor in registration with the area of topography and in close proximity to each other,wherein a depression in the area of topography causes a resistance between two runs of conductor overlying the depression to be lower than a resistance between two runs of conductor when no defect is in the area of topography.
1 Assignment
0 Petitions
Accused Products
Abstract
An integrated circuit wafer topography monitor is disclosed for sensing mis-processing in the fabrication of integrated circuits. In particular, the monitor senses unacceptable variations in layer planarity resulting from over polishing, over etching, scratches and mishandling. The topography monitor may be placed within the chip active area, the chip kerf area or in unutilized areas of the wafer such as a partial chip site. The monitor is formed when, first a conformal insulator is deposited over the topography of interest. Then, runs of wire are formed in the conformal insulator by a damascene or similar process. The wire runs are formed directly above the topography of interest. A puddle of metal is formed corresponding to any unacceptably non-planar topography. The puddle electrically couples the wires together. This effects a change in the metal runs which may be sensed as an electrical short or change in resistance. The topography of interest is manipulated by design to be representative of corresponding pattern factors found in the active chip area. This then allows the electrically sensed puddles to be indicative of mis-processing to be found in the active chip area.
35 Citations
12 Claims
-
1. A topography monitor for an integrated circuit chip wafer comprising:
-
an area of topography, a conformal insulator layer applied over the area of topography, and a conductive layer fabricated as a pattern in the conformal insulator layer, where the pattern is intended by design to produce two or more runs of conductor in registration with the area of topography and in close proximity to each other, wherein a depression in the area of topography causes a resistance between two runs of conductor overlying the depression to be lower than a resistance between two runs of conductor when no defect is in the area of topography. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A topography monitor for monitoring a process profile in an area of topography comprising:
-
a substrate, an area of topography upon the substrate, a conformal insulator layer applied over the area of topography, and a conductive layer fabricated as a pattern upon the conformal insulator layer, where the pattern is intended by design to produce two or more runs of conductor in registration with the area of topography and in close proximity to each other and running over the area of topography, wherein the electrical characteristic of the runs of conductor indicates the process profile, so that a depression in the area of topography causes a resistance between two runs of conductor overlying the depression to be lower than a resistance between two runs of conductor when no defect is present in the area of topography. - View Dependent Claims (11, 12)
-
Specification