Memory device with improved charge storage barrier structure

• US 5,952,692 A
• Filed: 10/28/1997
• Issued: 09/14/1999
• Est. Priority Date: 11/15/1996
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sato, Toshihiko, Itoh, Kiyoo, Ahmed, Haroon, Nakazato, Kazuo, Shimada, Toshikazu, Mizuta, Hiroshi
• Primary Examiner(s): Hardy, David B.
• Application Number:
  US08/958,845
• Time in Patent Office: 686 Days
• Field of Search: 257/321, 257/324, 257/316, 257/635, 257/636, 257/637, 257/649, 257/28, 257/325, 257/410, 257/411, 438/261, 438/264
• US Class Current: 257/321
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 13/02 using elements whose operation depends upon chemical change G11C13/0009 takes precedence
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/28229 by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/7888 Transistors programmable by two single electrons

Abstract

A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si₃ N₄ of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.

Claims

1. A memory device comprising a path for charge carriers, a node for storing charge to produce a field which alters the conductivity of the path, an electrode structure, and a tunnel barrier configuration through which charge carriers tunnel from the electrode structure to the node and vice versa in response to given voltages so as to become stored on and discharged from the node, the tunnel barrier configuration exhibiting an energy band profile that comprises a dimensionally relatively wide barrier component with a relatively low barrier height, and at least one dimensionally relatively narrow barrier component with a relatively high barrier height.

2. A memory device according to claim 1 wherein the component of the energy band profile of relatively high barrier height is provided by an element of a width of 3 nm or less.

3. A memory device according to claim 1 wherein the energy band profile of the tunnel barrier configuration includes a plurality of said relatively high barrier height components.

4. A memory device according to claim 1 wherein the barrier configuration comprises a multiple tunnel junction configuration.

5. A memory device according to claim 3 wherein the configuration includes alternate layers of relatively electrically conductive and insulating material wherein the layers collectively provide said relatively low barrier height component of the energy band profile, and the individual insulating layers provide the relatively high barrier components.

6. A memory device according to claim 5 wherein the alternate layers comprise polysilicon and silicon nitride respectively.

7. A memory device according to claim 5 wherein the electrically conductive layers each are of a thickness of less than 10 nm and the insulating layers are of a thickness of the order of 2 nm.

8. A memory device according to claim 1 wherein the barrier configuration comprises a Schottky barrier configuration.

9. A memory device according to claim 8 wherein the configuration includes alternate layers of electrically conductive material and semiconductor material.

10. A memory device according to claim 1 wherein the charge storage node comprises a layer of electrically conductive material between the barrier configuration and said path.

11. A memory device according to claim 10 wherein the layer comprises doped semiconductor material.

12. A memory device according to claim 1 wherein the charge storage node comprises a plurality of conductive islands.

13. A memory device according to claim 12 wherein the islands are distributed in the barrier configuration.

14. A memory device according to claim 13 wherein the islands have a diameter of 5 nm or less.

15. A memory device according to claim 13 wherein the islands give rise to relatively narrow, low barrier components of said energy band profile between said relatively high components.

16. A memory device according to claim 12 wherein the islands are arranged in layers separated by electrically insulating material.

17. A memory device according to claim 16, wherein the spacing of the layers is less than 3 nm.

18. A memory device according to claim 17 wherein the islands have a diameter of the order of 3 nm and the spacing of the layers is of the order of 2 nm.

19. A memory device according to claim 12 wherein the islands comprise nano-crystals of semiconductor material.

20. A memory device according to claim 12 wherein the islands are of a metal.

21. A memory device according to claim 20 wherein the metallic islands have been formed by sputtering and are distributed in an insulating metallic oxide.

22. A memory device according to claim 12 wherein the islands comprise particles deposited from a liquid suspension.

23. A memory device according to claim 1 wherein the tunnel barrier configuration exhibits a blocking voltage range (V_B) in which charge carrier tunnelling to the node is blocked, and including control structure operative to increase and decrease the blocking voltage range to control the amount of charge stored in the node.

24. A memory device according to claim 23 wherein the charge storage node is configured to store charge in a plurality of discrete states.

25. A memory device according to claim 24 wherein the control structure is operative to raise and lower the blocking voltage range so as to permit only a selected one of the states to exist at the node.

26. A memory device according to claim 23 wherein the control structure is operative to vary the width of the voltage blocking range.

27. A memory device according to claim 23 wherein the control structure is operative to lower the height of the relatively wide barrier component so that charge tunnels through the or each said relatively narrow barrier component to become stored in the node, and the control structure is operative to raise the height of the relatively wide barrier component so that charge stored in the node is inhibited from tunnelling through the barrier configuration.

28. A memory device according to claim 27 wherein the control structure is operative to apply to the barrier configuration a write voltage for causing charge tunnelling to the node, a read voltage greater than the write voltage for permitting data to be read from the device selectively, and a standby voltage greater than the read voltage, for inhibiting charge tunnelling from the node.

29. A memory device according to claim 1 including a control electrode from which charge carriers tunnel through the barrier configuration to the node in response to a given voltage applied thereto.

30. A memory device according to a claim 1 including a single one of said relatively narrow barrier components with a width greater than 3 nm.

31. A memory device according to claim 30 wherein said single barrier component is formed by a layer of Si₃ N₄ sandwiched between layers of undoped Si.

32. A memory device according to claim 1 including a gate electrode for applying an electric field to the tunnel barrier configuration to alter the barrier configuration thereof.

33. A memory device according to claim 1 wherein the amount of charge that can be stored on the charge storage node is limited by the Coulomb blockade effect.

34. A memory device according to claim 1 including source and drain regions coupled to the path.

35. A memory device including a plurality of memory devices each according to claim 1, defining an array of memory cells in rows and columns in a common substrate.

36. A memory device according to claim 35 including source and drain lines coupled to the respective paths of the columns of cells, and word lines extending along the rows of the cells for controlling the tunnelling of charge through the barrier configurations of the cells.

37. A memory device according to claim 35 including circuits for selectively reading stored data from the cells individually, and for refreshing the stored data.

38. A memory device according to claim 37 including data circuitry for selectively storing data in the cells individually.

39. A memory device according to claim 35 including sensing lines for detecting current flowing in the paths of respective columns of the memory cells, word lines, data lines for controlling the barrier configurations of the memory cells of a respective column thereof, a precharge circuit for precharging the sensing lines, the sensing lines taking up a charge level dependent upon the stored charge at the charge storage node of a particular one of the cells in a column thereof read in response to a read voltage applied to a corresponding word line, a read/write circuit for transferring the voltage level of the sensing line to the corresponding word line for the column, data output circuitry responsive to the voltage level on the data line for providing a data output corresponding to the stored data in the read cell, and data refreshing circuitry for applying a write voltage to the word line of the read cell such that data corresponding to the voltage level on the data line is written back into the previously read cell.

40. A memory device according to claim 39 including circuitry for changing the level of voltage on the data line after operation of the read/write circuit in response to input data to be written into the cell, whereby the write voltage causes the input data to be written to the cell.

41. A memory device according to any one of claims 35 wherein the array includes peripheral circuits formed on a common substrate with the memory cells.

42. A memory device according to claim 41 wherein the peripheral circuits include transistors that include regions formed by the same process steps that are used to form corresponding regions in the cells of the array.

43. A memory device according to claim 1 wherein the electrode structure comprises a single line overlying the tunnel barrier configuration.

44. A method of fabricating a memory device which includes a path for charge carriers, a node for storing charge that alters the conductivity of the path, an electrode structure and a tunnel barrier configuration through which charge carriers tunnel from the electrode structure to the node and vice versa in response to given voltages so as to become stored on and discharged from the node, the method including forming the tunnel barrier configuration such that it exhibits an energy band profile that comprises a dimensionally relatively wide barrier component with a relatively low barrier height, and at least one dimensionally relatively narrow barrier component with a relatively high barrier height.

45. A method according to claim 44 including forming the tunnel barrier configuration from regions of relatively conductive and insulating material.

46. A method according to claim 45 including forming said regions as overlying layers.

47. A method according to claim 46 including forming an insulating layer with a thickness of 3 nm or less.

48. A method according to claim 46 including forming a conductive layer with a thickness of 10 nm or less.

49. A method according to claim 46 including providing a layer of silicon to form the conductive layer and treating the surface thereof to form the insulating layer.

50. A method according to claim 49 including nitriding the surface of the silicon layer to form the insulating layer.

51. A method according to claim 44 including forming the node as a layer of conductive material.

52. A method according to claim 44 including forming the node as a of plurality of conductive islands.

53. A method according to claim 52 including distributing the islands in the barrier configuration.

54. A method according to claim 52 including forming the islands of semiconductor material.

55. A method according to claim 52 including forming the islands by sputtering.

56. A method according to claim 52 including depositing the islands from a liquid suspension.

57. A method according to claim 44 including forming a gate electrode for applying an electric field to the tunnel barrier configuration to control the barrier configuration thereof.

58. A method according to claim 44 including forming source and drain regions coupled to the path.

59. A method according to claim 44 including forming a plurality of the memory devices as memory cells in an array in a common substrate.

60. A method according to claim 59 including forming peripheral circuits for reading and writing data to and from the array in said common substrate.

61. A memory device fabricated by a method as claimed in claim 44.

62. A memory device comprising a path for charge carriers, a node for storing charge to produce a field which alters the conductivity of the path, and a tunnel barrier configuration through which charge carriers tunnel in response to a given voltage so as to become stored on the node, the tunnel barrier configuration exhibiting an energy band profile that comprises a dimensionally relatively wide barrier component with a relatively low barrier height, and at least one dimensionally relatively narrow barrier height, wherein the charge storage nodes comprises a plurality of conductive islands distributed in the barrier configuration.

63. A memory device comprising:

a source-drain path for charge carriers,

a node for storing charge to produce a field which alters the conductivity of the source-drain path,

an electrode structure overlying the node, and

a tunnel barrier configuration between the node and the electrode structure through which charge carriers tunnel between the electrode structure and the node in response to given voltages so as to become stored on and discharged from the node, the tunnel barrier configuration comprising a layer of relatively conductive polysilicon material, a first layer of relatively non-conductive silicon nitride between the polysilicon layer and the node, and a second layer of relatively non-conductive silicon nitride between the polysilicon layer and the electrode structure, the tunnel barrier configuration exhibiting an energy band profile that comprises a dimensionally relatively wide barrier component with a relatively low barrier height, and at least one dimensionally relatively narrow barrier component with a relatively high barrier height.