MOSFET device with unsymmetrical LDD region

• US 5,952,700 A
• Filed: 10/24/1997
• Issued: 09/14/1999
• Est. Priority Date: 09/06/1997
• Status: Expired due to Term

• Current Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Original Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Inventors: Yoon, Gyu Han
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US08/957,622
• Time in Patent Office: 690 Days
• Field of Search: 257/405, 257/406, 257/408, 257/410, 257/411, 438/287
• US Class Current: 257/405
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device is disclosed, including: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a first region including one edge of the gate electrode; a second gate insulating layer formed between the gate electrode and semiconductor substrate, and formed at a second portion including the other edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer; a first impurity region formed in a predetermined portion of the semiconductor substrate, placed on both sides of the gate electrode; and a second impurity region formed in a predetermined portion of the semiconductor substrate, placed under the second gate insulating layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a gate electrode formed on the semiconductor substrate;

a first gate insulating layer formed between the gate electrode and the semiconductor substrate, and formed at a first region including a first edge of the gate electrode;

a second gate insulating layer formed between the gate electrode and the semiconductor substrate, and formed at a second region including a second edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer, and the second gate insulating layer containing impurity ions and the first gate insulating layer containing no implanted impurity ions;

first impurity regions formed in the semiconductor substrate on both sides of the gate electrode; and

a second impurity region formed in the semiconductor substrate positioned only under the second gate insulating layer.

2. The semiconductor device as claimed in claim 1, wherein the second gate insulating layer includes an upper insulating layer and a lower insulating layer.

3. The semiconductor device as claimed in claim 2, wherein the semiconductor substrate has a first conductivity type, the lower insulating layer is doped with impurity ions having the first conductivity type, and the upper insulating layer is doped with impurity ions having a second conductivity type.

4. The semiconductor device as claimed in claim 3, wherein the lower insulating layer is doped with p-type impurity ions, and the upper insulating layer is doped with n-type impurity ions.

5. The semiconductor device as claimed in claim 1, wherein the first gate insulating layer is wider than the second gate insulating layer.

6. The semiconductor device as claimed in claim 1, wherein the semiconductor substrate has a first conductivity type, and the first and second impurity regions have the second conductivity type.

7. The semiconductor device as claimed in claim 6, wherein the second impurity region has a concentration of impurity ions lower than that of the first impurity regions.

8. The semiconductor device as claimed in claim 1, further comprising a third impurity region formed in a portion of the semiconductor substrate, the portion coming into contact only with the second impurity region.

9. The semiconductor device as claimed in claim 8, wherein the semiconductor substrate and the third impurity region both have a first conductivity type.

10. A semiconductor device comprising:

a semiconductor substrate of a p-type conductivity;

a gate electrode on the semiconductor substrate;

a first insulating layer between the gate electrode and the semiconductor substrate at a first region including a first edge of the gate electrode;

a second gate insulating layer between the gate electrode and the semiconductor substrate at a second region including a second edge of the gate electrode, the second gate insulating layer being thicker than the first gate insulating layer, and the second gate insulating layer containing impurity ions and the first gate insulating layer containing no implanted impurity ions;

first impurity regions of a n-type conductivity in the semiconductor substrate on both sides of the gate electrode;

a second impurity region of the p-type conductivity in the semiconductor substrate positioned under the second gate insulating layer; and

a third impurity region of the n-type conductivity in a portion of the semiconductor substrate, the portion coming into contact with the second impurity region.