Inductor devices using substrate biasing technique

• US 5,952,704 A
• Filed: 04/17/1997
• Issued: 09/14/1999
• Est. Priority Date: 12/06/1996
• Status: Expired due to Term

• Current Assignee: Intellectual Discovery Co., Ltd.
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Yu, Hyun-Kyu, Park, Min, Kim, Cheon-Soo, Nam, Kee-Soo
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US08/842,869
• Time in Patent Office: 880 Days
• Field of Search: 257/528, 257/531, 257/774, 257/513
• US Class Current: 257/531
• CPC Class Codes: H01F 2017/0046 with a conductive path having a bridge
• CPC Class Codes: H01L 28/10 Inductors

Abstract

Inductors used for impedance matching in the radio frequency integrated circuits is disclosed. In the integrated inductor device according to the present invention, an additional electrode is arranged in surroundings of an inductor metal line, and the reverse bias voltage is applied to the region between the substrate and the electrode so as to form a depletion layer. Therefore, the substrate biasing is effected and thus an inductor having improved performance can be formed by decreasing the parasitic capacitance between the inductor metal line and the substrate. The present invention can also be applied to another semiconductor device having metal lines and pads.

Claims

1. An inductor device formed in a semiconductor substrate having a conductivity due to doping in the form of an integrated circuit, which comprises:

a first metal line formed on said semiconductor substrate in the form of a coil;

a second metal line for applying a predetermined voltage to said first metal line;

a first connecting means for connecting said first metal line to said second metal line;

an electrode having a trench shape formed in said semiconductor substrate, on a bottom portion of said first metal line as seen from the above thereof,

a third metal line for applying a predetermined voltage to said electrode;

a second connecting means for connecting said electrode to said third metal line;

a fourth metal line for applying a predetermined voltage to said semiconductor substrate; and

a third connecting means for connecting said semiconductor substrate to said fourth metal line, and

a reverse bias voltage is applied between said semiconductor substrate and said electrode.

2. The inductor device of claim 1, wherein said electrode comprises a doped polysilicon layer doped with dopants of a conductivity which is the opposite conductivity to the dopants in said semiconductor substrate.

3. The inductor device of claim 1, wherein

said electrode comprises a diffusion layer formed in said semiconductor substrate.

4. The inductor device of claim 2, wherein said electrode is N-type and said semiconductor substrate is P-type.

5. The inductor device of claim 3, wherein said electrode is N-type and said semiconductor substrate is P-type.

6. The inductor device of claim 4, which comprises said semiconductor substrate being grounded and said electrode being applied with the positive voltage.