Logic isolator with high transient immunity

• US 5,952,849 A
• Filed: 02/21/1997
• Issued: 09/14/1999
• Est. Priority Date: 02/21/1997
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Haigh, Geoffrey T.
• Primary Examiner(s): Santamauro, Jon
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/805,075
• Time in Patent Office: 935 Days
• Field of Search: 326/30, 326/56-58, 326/82, 326/86, 326/90
• US Class Current: 326/82
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 25/493 by transition coding, i.e. the time-position or direction of a transition being encoded before transmission

Abstract

A logic isolation circuit with high transient immunity has a link-coupled transformer assembly for providing isolation. An input circuit provides pulses that indicate rising and falling edges, and an output circuit on the isolated side of the barrier converts the signal with pulses back into a digital logic signal with rising and falling edges. An interrogation feature allows the output to be updated frequently. The logic isolator can be provided in a single module for use in a process control board, or it can be provided as multiple parts for mounting on a circuit board.

Claims

1. A logic isolator for isolating digital logic signals, the isolator comprising:

a transmit circuit for receiving a digital logic signal with rising and falling edges, the transmit circuit having edge detection circuitry for providing pulses that indicate relative locations in time of the rising and falling edges, the transmit circuit providing these pulses as a transmit output signal;

a transformer assembly including;

a first core,

a first winding wrapped around the first core for receiving the transmit output signal,

a second core,

a second winding wrapped around the second core for providing a transformer output signal that is substantially similar to the transmit output signal, and

a grounded link wire extending through the first core and the second core for grounding common mode transient signals received from the first winding of the transformer assembly; and

a receive circuit for receiving the transformer output signal, and including circuitry for converting pulses in the transformer output signal into an isolated output signal with rising and falling edges at substantially the same relative locations as the rising and falling edges in the digital logic signal.

2. The isolator of claim 1, wherein the transmit circuit converts rising and falling edges to pulses with tri-level logic, with a first level indicating a rising edge, a second level indicating a falling edge, and a third level indicating neither the rising edge nor the falling edge.

3. The isolator of claim 1, wherein the transmit circuit further includes a pulse generator for providing pulses with a width similar to a width of the pulses indicating the rising and falling edges, the pulses indicating a DC level of the digital logic signal and being provided to the transformer assembly.

4. The isolator of claim 3, wherein the isolator includes circuitry that inhibits a further one of the pulses from being provided to the transformer assembly for some time after an edge is detected.

5. The isolator of claim 4, wherein a single one of the pulses is inhibited, such that if the period of the pulses is T, a pulse is provided at a time t after an edge is detected, with T<

t<

2T.

6. The isolator of claim 3, wherein the receive circuit is responsive to the pulses from the pulse generator for determining the DC level of the digital logic signal.

7. The isolator of claim 1, wherein the transmit circuit is on a first side of the transformer assembly and receives the digital input signal from a first lead, and the receive circuit is on a second side of the transformer assembly and provides the receive output signal to a second lead, the isolator further comprising a receive circuit on the first side and coupled to receive a signal from the first winding and to provide a signal to the first lead, and a transmit circuit on the second side and coupled to provide a signal to the second winding and to receive a signal from the second lead, the transmit and receive circuits on each of the first and second sides being enabled and disabled by control signals.

8. The isolator of claim 7, wherein at least one of the control signals is provided in a changeable manner.

9. The isolator of claim 7, wherein at least one of the control signals is provided from a hard-wired connection.

10. The isolator of claim 1, wherein the transmit circuit includes a Schmitt trigger for receiving the digital input signal, and a transparent latch for receiving an output signal from the Schmitt trigger and for providing a latched signal to the edge detection circuitry.

11. The isolator of claim 1, wherein there is a plurality of transmit circuits, a plurality of respective transformer assemblies, and a plurality of respective receive circuits housed together in a single module.

12. The isolator of claim 1, comprising a plurality of substantially similar transmit circuits, transformer assemblies, and receive circuits.

13. A logic isolator for isolating digital logic signals comprising:

an input circuit for detecting rising and falling edges in an input digital logic signal, and for providing an output signal indicative of relative locations of the rising and falling edges;

a transformer assembly with a shielded single transformer for receiving the output signal from the input circuit and for providing a signal similar to the signal received by the transformer; and

an output signal circuit for receiving the signal from the transformer and for providing an output signal with rising and falling edges in the same relative locations as the rising and falling edges in the input digital logic signal.

14. The isolator of claim 13, wherein the transformer assembly includes a first core with a first winding, a second core with a second winding, and a grounded link wire having a portion around the first core and a portion around the second core for grounding common mode transients across the first winding while passing the inductively coupled input digital logic signal.

15. The isolator of claim 13, wherein the transformer assembly includes a first winding, a shield around the first winding, and a second winding around the shield and around the first winding, the first winding being a driven winding, the second winding being a receiving winding, and the shield grounded at the receiving side.

16. The isolator of claim 13, wherein the transformer assembly includes a first winding, a second winding, and two shields between the windings, with one shield being grounded to each side of the isolation barrier.

17. The isolator of claim 13, further comprising means for providing a periodic signal indicating a DC level of the input logic signal.

18. A method for logically isolating a digital logic signal comprising:

providing to a first side of an isolation barrier edge pulses indicative of rising and falling edges in a digital logic signal;

periodically generating refresh pulses with a pulse width equal to a pulse width of the edge pulses, the refresh pulses indicating a DC level of the digital logic signal;

providing the refresh pulses to the first side of the isolation barrier;

receiving a signal with edge pulses and refresh pulses on a second side of the isolation barrier; and

converting the received signal to an output digital logic signal that indicates relative locations of rising and falling edges in the digital logic signal.

19. The method of claim 18, further comprising a step of inhibiting at least one refresh pulse from being provided to the first side of the transformer after an edge pulse is provided.

20. The method of claim 19, wherein the inhibiting step includes inhibiting one refresh pulse such that if the refresh pulses have a period T, a refresh pulse is provided at time t after an edge, with T<

t<

2T.

21. The method of claim 18, wherein the providing includes providing the refresh pulses with at least three logic levels, with a first level indicating a rising edge, a second level indicating a falling edge, and a third level indicating neither a rising edge nor a falling edge.

22. The method of claim 18, wherein the pulses are provided to a transformer assembly as the isolation barrier.

23. A digital logic isolator comprising:

a transmit circuit for receiving an input digital logic signal and including edge detection circuitry for converting rising and falling edges of the input digital logic signal into edge pulses having a pulse width, the transmit circuit providing a transmit output signal with the edge pulses;

a pulse generator for providing refresh pulses at a desired frequency, the refresh pulses indicating a DC level of the input digital logic signal;

an isolation barrier for receiving the edge pulses and the refresh pulses and for providing an isolated output signal with the edge pulses and the refresh pulses; and

a receive circuit for receiving the isolated output signal and for using the edge pulses to produce an output digital logic signal with rising and falling edges at relative locations that are the same as the rising and falling edges in the input digital logic signal.

24. The isolator of claim 23, wherein the refresh pulses are logically combined with the edge pulses such that the receive circuit can use the refresh pulses to determine changes in the state of the digital logic signal even if the receive circuit does not receive a prior edge pulse indicating a rising or falling edge.

25. The isolator of claim 23, wherein the transmit circuit has circuitry for preventing pulses from the pulse generator from being provided across the isolation barrier for a period of time after a refresh pulse due to a rising or falling edge.

26. The isolator of claim 25, wherein the circuitry for preventing pulses prevents one pulse after a rising or falling edge, so that a next refresh pulse is provided at a time t after an edge, with T<

t<

2T, where T is the period of the refresh pulses.

27. The isolator of claim 23, wherein the isolation barrier includes a transformer assembly with a shielded single transformer.

28. The isolator of claim 23, wherein the isolation barrier includes a transformer assembly with a first core, a first winding around the first core, a second core, and a grounded link wire extending from the first core to the second core.

29. The isolator of claim 23, wherein the pulse generator includes two pulse generating units, one of which generates pulses in response to a high DC level, the other of which generates pulses in response to a low DC level.

30. The isolator of claim 29, wherein each pulse generating unit generates pulses with a period T, the pulse generating units generating pulses beginning at a time t=T after a respective rising or falling edge is detected.