Roving range control to limit receive PLL frequency of operation
First Claim
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1. A circuit comprising:
- a plurality of phase locked loop circuits each configured to present a recovered data signal and a recovered clock signal in response to (i) one of a plurality of serial data streams, (ii) an input clock signal, and (iii) one of a plurality of indication signals;
a control circuit configured to present a counter signal in response to a ratio of each of said recovered clock signals to said input clock signal; and
a plurality of storage elements each configured to present one of said plurality of indication signals in response to (i) said input clock signal and (ii) a select signal and (iii) said counter signal.
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Abstract
A circuit comprising a plurality of phase locked loop circuits, a control circuit and a plurality of storage elements. Each of the plurality of phase locked loop circuits may present a recovered data signal and a recovered clock signal in response to one of a plurality of serial data streams, a clock signal and one of a plurality of indication signals. The control circuit may present a counter signal in response to the recovered clock signals. The plurality of storage elements may each be configured to present one of the indication signals in response to the clock signal, a select signal and the counter signal.
82 Citations
17 Claims
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1. A circuit comprising:
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a plurality of phase locked loop circuits each configured to present a recovered data signal and a recovered clock signal in response to (i) one of a plurality of serial data streams, (ii) an input clock signal, and (iii) one of a plurality of indication signals; a control circuit configured to present a counter signal in response to a ratio of each of said recovered clock signals to said input clock signal; and a plurality of storage elements each configured to present one of said plurality of indication signals in response to (i) said input clock signal and (ii) a select signal and (iii) said counter signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A circuit comprising:
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a plurality of phase locked loop circuits each configured to present a recovered data signal and a recovered clock signal in response to (i) one of a plurality of serial data streams, (ii) a clock signal, and (iii) one of a plurality of indication signals; means for generating a counter signal in response to a ratio of each of said recovered clock signals to said input clock signal; and means for generating one of said plurality of indication signals in response to (i) said clock signal and (ii) a select signal and (iii) said counter signal.
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10. A method for limiting the frequency of operation of a circuit, comprising the steps of:
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(a) generating a recovered data signal and a recovered clock signal in response to (i) one of a plurality of serial data streams, (ii) an input clock signal, and (iii) one of a plurality of indications signals; (b) generating a counter signal in response to a ratio of each of said recovered clock signals to said input clock signal; and (c ) generating each of said plurality of indication signals in response to (i) said input clock signal and (ii) a select signal and (iii) said counter signal. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification