Method and apparatus for implementing engineering change orders in integrated circuit designs

• US 5,953,236 A
• Filed: 10/31/1995
• Issued: 09/14/1999
• Est. Priority Date: 10/31/1995
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Thumma, Bala, Ashtaputre, Sunil, Hossain, Moazzem
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/550,848
• Time in Patent Office: 1,414 Days
• Field of Search: 364/488-491, 364/578
• US Class Current: 716/104
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool includes the steps of: (a) placing cells specified by the netlist in a layout area in a placement step, the cells including pins that are interconnected by nets; (b) verifying timing constraints in a timing verification step of the placed cells in the layout area; and (c) if the timing verification step indicates that timing does not verify in that the timing constraints are not met: (i) modifying the netlist pursuant to an engineering change order (ECO); and (ii) making an ECO placement of at least one cell into the layout area based upon the timing constraints while adjusting any affected nets as specified by the netlist. A layout tool implements the method on a computer system to form a portion of and integrated circuit fabrication system.

Claims

1. A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool, said method comprising the steps of:

A) receiving into a computer readable memory said netlist provided by said behavioral synthesis tool specifying cells and cell interconnections satisfying constraints of said integrated circuit design;

B) placing cells specified by said netlist in a layout area in a placement step, said cells including pins that are interconnected by nets;

(C) verifying timing constraints in a timing verification step of said placed cells in said layout area, such that said timing verification step accounts for an allowed delay on a critical path defined by a sequence of said pins that are interconnected by said nets; and

(D) if said timing verification step indicates that timing does not verify in that said timing constraints are not within certain tolerance;

(a) modifying said netlist pursuant to an engineering change order (ECO), said netlist reflecting a change in said placed cells that include pins that are interconnected by nets; and

(b) making an ECO placement of at least one cell into said layout area that comprises said placed cells, the making of said ECO placement being configured to meet said timing constraints that are verified in the timing verification step that accounts for said allowed delay on said critical path, and said placement of said at least one cell being performed while adjusting any affected nets of said netlist, the placement comprising the steps of;

(1) determining a target window said layout area for the placement of said picked cell, said target window being a subset of said layout area, said target window representing the portion of the integrated circuit layout area that will be modified to implement said ECO;

(2) picking an unplaced cell from a set of unplaced cells to be a picked cell;

mapping said picked cell inside said target window;

(4) removing said picked cell from said set of unplaced cells;

(5) optimizing the placement of said picked cell by analyzing said picked cell within said target window with respect to said placed cells, and modifying said placement of said picked cell with respect to said placed cells if modifying said placement of said picked cell improves timing; and

(6) repeating steps (1)-(5) until said set of unplaced cells is empty, whereby said cell layout is modified to represent said ECO without having to entirely recreate said cell layout; and

(E) repeating steps (C) and (D) until said timing constraints are met within said certain tolerance.

2. A method as recited in claim 1 wherein said step of determining said target window involves determining a minimum bounding box that encloses pins connected by nets of cells within the set of unplaced cells.

3. A method as recited in claim 2 wherein said step of determining said target window further involves using weights assigned said nets of said set of unplaced cells, said weights being related to timing constraints of said integrated circuit design.

4. A method as recited in claim 3 wherein said mapping step for a gate array includes the steps of:

mapping said cell to an empty site in said target window, if one exists; and

if no empty site exists in said target window, mapping said cell to a site in said window that would exhibit a minimum of overlap with adjacent cells, and moving any overlapped adjacent cells locally within the layout area until the overlap has been eliminated.

5. A method as recited in claim 3 wherein said mapping step for a standard cell includes the steps of:

mapping said cell to a row of cells within said window;

pushing any cells in that row to remove any overlap; and

if said row no longer fits within the target window, removing a cell from said row and placing it in another row.

6. A method for making an integrated circuit comprising the steps of:

(A) creating a hardware description language (HDL) description of the functionality of said integrated circuit;

(B) synthesizing a netlist from said HDL description;

(C) laying out a design of said integrated circuit by;

(a) placing cells specified by said netlist in a layout area in a placement step, said cells including pins that arm interconnected by nets;

(b) verifying timing constraints in a timing verification step of said placed cells in said layout area, such that said timing verification step accounts for an allowed delay on a critical path defined by a sequence of said pins that are interconnected by said nets;

(c) if said timing verification step indicates that timing does not verify in that said timing constraints are not within a certain tolerance;

(i) modifying said netlist pursuant to an engineering change order (ECO), said netlist reflecting a change in said placed cells that include pins that are interconnected by nets; and

(ii) making an ECO placement of at least one cell into said layout area that comprises said placed cells, the making of said ECO placement being configured to meet said timing constraints that are verified in the timing verification step that accounts for said allowed delay on said critical path, and said placement of said at least one cell being performed while adjusting any affected nets of said netlist, the placement comprising the steps of;

(1) determining a target window within said layout area for the placement of said picked cell, said target window being a subset of said layout area, said target window resenting that portion of the integrated circuit layout area that will be modified to implement said ECO;

(2) picking an unplaced cell from a set of unplaced cells to be a picked cell;

(3) mapping said picked cell inside said target window;

(4) removing said picked cell from said set of unplaced cells;

(5) optimizing the placement of said picked cell by analyzing said picked cell within said target window with respect to said placed cells, and modifying said placement of said picked cell with respect to said placed cells if modifying said placement of said picked cell improved timing; and

(6) repeating steps (1)-(5) until said set of unplaced cells is empty, whereby said cell layout is modified to represent said ECO without hat to entirely recreate said cell layout; and

(d) repeating steps (b) and (c) until said timing constraints are met within said certain tolerance;

(e) routing between the placed cells in said layout area; and

(f) creating a mask layout description from said placed and routed cells;

(D) creating at least one mask from said mask layout description; and

(E) producing at least one integrated circuit utilizing said at least one mask.

7. A method as recited in claim 6 wherein said step of determining said target window involves determining a minimum bounding box that encloses pins connected by nets of cells within the set of unplaced cells.

8. A method as recited in claim 7 wherein said step of determining said target window further involves using weights assigned said nets of said set of unplaced cells, said weights being related to timing constraints of said integrated circuit design.

9. A method as recited in claim 8 wherein said mapping step for a gate array includes the steps of:

mapping said cell to an empty site in said target window, if one exists; and

if no empty site exists in said target window, mapping said cell to a site in said window that would exhibit a minimum of overlap with adjacent cells, and moving any overlapped adjacent cells locally within the layout area until the overlap has been eliminated.

10. A method as recited in claim 8 wherein said mapping step for a standard cell includes the steps of:

mapping said cell to a row of cells within said window;

pushing any cells in that row to remove any overlap; and

if said row no longer fits within the target window, removing a cell from said row and placing it in another row.

11. An integrated circuit layout tool comprising:

a computer system including a central processing unit (CPU) and computer readable memory coupled to said CPU;

(A) means for receiving into memory a netlist describing an integrated circuit design;

(B) means for placing cells specified by said netlist in a layout area of said integrated circuit design, said cells including pins that are interconnected by nets;

(C) means for verifying timing constraints of said placed cells in said layout area, such that said means for verifying timing constraints accounts for an allowed delay on a critical path defined by a sequence of said pins that are interconnected by said nets; and

(D) if said timing constraints are not verified by said means for verifying timing constraints to be within a certain tolerance, then;

(a) means for modifying said netlist pursuant to an engineering change order (ECO) said netlist reflecting a change in said placed cells that include pins that are interconnected by nets; and

(b) means for making an ECO placement of at least one cell into said layout area that includes said placed cells, the means for making an ECO placement being configured to meet said timing constraints that are verified by said means for verifying timing constraints which accounts for said allowed delay on said critical, path and said placement of said at least one cell being performed while adjusting any affected nets as specified by said netlist, the means for making an ECO placement comprising;

(1) means for determining a target window within said layout area for the placement of said picked cell, said target window being a subset of said layout area, said target window representing that portion of the ingrated circuit layout area will be modified to implement said ECO;

(2) means for picking an unplaced cell from a set of unplaced cells to be a picked cell;

(3) means for mapping said picked cell inside said target window;

(4) means for removing said picked cell from said set of unplaced cells;

(5) means for optimizing the placement of said picked cell by analyzing said picked cell within said target window with respect to said placed cells, and modifying said placement of said picked cell with respect to said placed cells if modifying said placement of said picked cell improves timing; and

(6) means for repeating steps (1)-(5) until said set of placed cells is empty, whereby said cell layout is modified to represent said ECO without having to entirely recreate said cell layout; and

(E) repeating steps (a) and (b) until said timing constraints are met within said certain tolerance.

12. A method as recited in claim 11 wherein said means for determining said target window utilizes a minimum bounding box that encloses pins connected by nets of cells within the set of unplaced cells.

13. An integrated layout tool as recited in claim 12 wherein said means for determining said target window further utilizes weights assigned said nets of said set of unplaced cells, said weights being related to timing constraints of said integrated circuit design.

14. An intergrated layout tool as recited in claim 13 wherein means for mapping for a gate array includes the steps of:

means for mapping said cell to an empty site in said target window, if one exists and, if not, means for mapping said cell to a site in said window that would exhibit a minimum of overlap with adjacent cells, and means for moving any overlapped adjacent cells locally within the layout area until the overlap has been eliminated.

15. An integrated circuit layout tool as recited in claim 13 wherein said means for mapping for a standard cell includes the steps of:

means for mapping said cell to a row of cells within said window;

means for pushing any cells in that row to remove any overlap; and

if said row no longer fits within the target window, means for removing a cell from said row and placing it in another row.

16. A method for laying out an integrated circuit design based upon a netlist provided by a behavioral synthesis tool, said method comprising:

(A) generating said netlist by said behavioral synthesis tool specifying cells and cell interconnections satisfying constraints of said integrated circuit design, said cells having pins that are interconnected by nets;

(B) placing cells specified by said netlist in a layout area in a placement step;

(C) verifying timing constraints in a timing verification step of said placed cells in said layout area; and

(D) if said timing verification step indicates that timing does not verify in that said timing constraints are not wit a certain tolerance;

(a) modifying said netlist pursuant to an engineering change order (ECO); and

(b) making an ECO placement of at least one cell into said layout area based upon said timing constraints while adjusting any affected nets as specified by said netlist said ECO placement comprising;

(i) picking an unplaced cell from a set of unplaced cells to be a picked cell;

(ii) determining a target window within said layout area for the placement of said picked cell;

(iii) mapping said picked cell inside said target window;

(iv) removing said picked cell from said set of unplaced cells; and

(v) repeating steps (i)-(iv) until said set of unplaced cells is empty;

(E) repeating steps (a) and (b) until said timing constraints are met within said certain tolerance.

17. A method as recited in claim 16, wherein said step of determining said target window involves determining a minimum bounding box that encloses pins connected by nets of cells within the set of unplaced cells.

18. A method as recited in claim 17 wherein said step of determining said target window further involves using weights assigned said nets of said set of unplaced cells, said weights being related to timing constraints of said integrated circuit design.

19. A method as recited in claim 18 wherein said mapping step for a gate array includes the steps of:

mapping said cell to an empty site in said target window, if one exists; and

if no empty site exists in said target window, mapping said cell to a site in said window that would exhibit a minimum of overlap with adjacent cells, and moving any overlapped adjacent cells locally within the layout area until the overlap has been eliminated.

20. A method as recited in claim 18 wherein said mapping step for a standard cell includes the steps of:

mapping said cell to a row of cells within said window;

pushing any cells in that row to remove any overlap; and

if said row no longer fits within the target window, removing a cell from said row and placing it in another row.

21. A computer readable medium storing a computer program suitable for laying out an integrated circuit design, said computer program comprising computer executable instructions for:

(A) receiving into memory a netlist specifying cells and cell interconnections satisfying constraints of said integrated circuit design, said cells having pins that are interconnected by nets;

(B) placing said cells specified by said netlist into a layout that is a representation of a physical layout area of said integrated circuit design;

(C) verifying timing constraints in a timing verification step of said placed cells in said layout area; and

(D) if said timing verification step indicates that timing does not verify in that said timing constraints are not within a certain tolerance;

(a) modifying said netlist pursuant to an engineering change order (ECO), said ECO representing an incremental change to said integrated circuit that is intended to bring said integrated circuit closer to said timing constraints; and

(b) making an ECO placement of at least one cell into said layout area by;

(1) determining a target window within said layout area for the placement of said picked cell, said target window being a subset of said layout area, said target window representing that portion of the integrated circuit layout area that will be modified to implement said ECO;

(2) picking an unplaced cell from a set of unplaced cells to be a picked cell;

(3) mapping said picked cell inside said target window;

(4) removing said picked cell from said set of unplaced cells;

(5) optimizing the placement of said picked cell by analyzing said picked cell within said target window with respect to said placed cells, and modifying said placement of said picked cell with respect to said placed cells if modifying said placement of said picked cell improves timing; and

(6) repeating steps (1)-(5) until said set of unplaced cells is empty, whereby said cell layout is modified to represent said ECO without having to entirely recreate said cell layout,

(E) repeating execution of (C) and (D) until said timing constraints are met within said certain tolerance.