Synchronous memory device having a programmable register and method of controlling same
DCFirst Claim
1. A synchronous semiconductor memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises:
- a programmable register to store a value which is representative of a delay time after which the memory device responds to a read request.
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Abstract
The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.
The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
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Citations
33 Claims
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1. A synchronous semiconductor memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises:
a programmable register to store a value which is representative of a delay time after which the memory device responds to a read request. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A synchronous semiconductor memory device having at least one memory section which includes a plurality of memory cells, the memory device comprising:
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a programmable register to store a value which is representative of a programmable delay time after which the memory device responds to a transaction request; and wherein the memory device responds to a first transaction request in accordance with a fixed delay time and, after programming the programmable register, responds to the second transaction request in accordance with the programmable delay time. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A synchronous semiconductor memory device having at least one memory section which includes a plurality of memory cells, the memory device comprising:
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a programmable register to store a value which is representative of a number of clock cycles of an external clock to transpire before data is output onto an external bus in response to a read request; and a plurality of output drivers, coupled to the bus, to output data in response to the read request, wherein the output drivers output data on the bus after the number of clock cycles of the external clock transpire. - View Dependent Claims (15, 16, 17)
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18. A method of controlling the operation of a synchronous semiconductor memory device wherein the memory device includes a register, the method comprising:
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providing a time delay value to the memory device; storing the time delay value in the register in the memory device, wherein the time delay value is representative of a time delay after which the memory device responds to a transaction request. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of operation of a semiconductor memory device wherein the memory device includes a programmable register, the method comprising:
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receiving a time delay value, wherein the time delay value is representative of a number of clock cycles of an external clock to transpire before data is output onto an external bus in response to a read request; and storing the time delay value in the register. - View Dependent Claims (28, 29)
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30. An integrated circuit device having memory including at least one memory section which includes a plurality of memory cells, the integrated circuit device comprising:
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a programmable register to store a value which is representative of a number of clock cycles of a clock to transpire before data is output onto a bus in response to a read request; and a plurality of output drivers, coupled to the bus, to output data in response to the read request, wherein the output drivers output data on the bus after the number of clock cycles of the clock transpire and synchronously with respect to the clock. - View Dependent Claims (31, 32, 33)
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Specification