Data processing apparatus

• US 5,953,416 A
• Filed: 03/20/1997
• Issued: 09/14/1999
• Est. Priority Date: 11/12/1996
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hasebe, Takayuki, Takenaka, Masahiko, Torii, Naoya
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): Callahan, Paul E.
• Application Number:
  US08/825,696
• Time in Patent Office: 908 Days
• Field of Search: 380/3, 380/4, 380/20-23, 380/25, 380/43, 380/48-49, 380/50, 341/20, 341/50, 341/173, 711/121, 711/152, 711/163-164, 340/825.31, 340/825.34, 348/5.5, 395/80-186, 395/200.3
• US Class Current: 713/189
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00

Abstract

A data processing apparatus serves as I/O units coupled to information processes apparatuses such as computers. The data processing apparatus decodes encrypted data and performs processing according to message data. The data processing apparatus includes a data processing circuit performing decoding processing and message processing according to message data, a data buffer accessible from both the data processing circuit and the information processing apparatus, a data buffer monitor circuit monitoring states of read/write of the data to the data buffer, and an access control circuit controlling an access from the information processing apparatus to the data buffer.

Claims

1. A data processing apparatus comprising:

a data processing circuit decoding encrypted data;

a data buffer connected to an external information processing apparatus, said data buffer being accessible from both said data processing circuit and said information processing apparatus; and

a data buffer monitor circuit informing said data processing circuit, when a write-in of data from said information processing apparatus into said data buffer occurs, of the fact that the write-in of data has occurred, and informing said information processing apparatus, when a write-in of data from said data processing circuit into said data buffer occurs, of the fact that the write-in of data has occurred.

2. A data processing apparatus according to claim 1, wherein said data monitor circuit informs said data processing circuit, when data written into said data buffer from said information processing apparatus are completely read out in its entirety by said data processing circuit, of the fact that all the data have been completely read out, and informing said information processing apparatus, when data written into said data buffer from said data processing circuit are completely read out in its entirety by said information processing apparatus, of the fact that all the data have been completely read out.

3. A data processing apparatus according to claim 1, wherein said data buffer comprises a first data buffer into which data are written from said information processing apparatus, the data stored in said first data buffer being read out by said data processing circuit, and a second data buffer into which data are written from said data processing circuit, the data stored in said second data buffer being read out by said information processing apparatus.

4. A data processing apparatus comprising:

a data processing circuit executing a processing according to message data requesting the processing;

a data buffer connected to an external information processing apparatus, said data buffer being accessible from both said data processing circuit and said information processing apparatus; and

an access control circuit controlling an access from said information processing apparatus to said data buffer,

wherein said data processing circuit reads out message data written into said data buffer from said information processing apparatus and executes the processing according to the message data thus read out, and when executing the processing according to the message data, instructs said access control circuit to inhibit an access from said information processing apparatus to said data buffer.

5. A data processing apparatus according to claim 4, wherein said data processing circuit provides processing such that, when message data written into said data buffer from said information processing apparatus is encrypted message data, the message data is decoded into plain text of message data and then the processing according to the message data is executed, and said data processing circuit instructs said access control circuit to inhibit an access from said information processing apparatus to said data buffer, prior to a decoding processing the encrypted message data.

6. A data processing apparatus according to claim 4, wherein said data processing circuit provides processing such that, when message data written into said data buffer from said information processing apparatus is message data with a signature, signature confirmation processing the message data is performed and then the processing according to the message data is executed, and said data processing circuit instructs said access control circuit to inhibit an access from said information processing apparatus to said data buffer, prior to the signature confirmation processing the message data.

7. A data processing apparatus according to claim 4, wherein said access control circuit optionally inhibits a write-in of data from said information processing apparatus into said data buffer.

8. A data processing apparatus according to claim 4, wherein said access control circuit optionally inhibits a read-out of data from said data buffer to said information processing apparatus.

9. A data processing apparatus according to claim 4, wherein said data processing circuit includes a processor executing a program, and while said access control circuit inhibits an access from said information processing apparatus to said data buffer, said data processing circuit executes processing according to the message data using said data buffer as a working area.

10. A data processing apparatus according to claim 9, wherein said data processing circuit erases data stored in at least a part of memory areas of said data buffer, after executing the processing according to the message data, and thereafter said data processing circuit instructs said access control circuit to release an inhibition of an access from said information processing apparatus to said data buffer.

11. A data processing apparatus comprising:

a data processing circuit executing processing according to message data requesting the processing; and

a data buffer connected to an external information processing apparatus, said data buffer being accessible from both said data processing circuit and said information processing apparatus,

wherein said data processing circuit comprises a local memory accessible from said data processing circuit but unaccessible from said information processing apparatus, and said data processing circuit transfers to said local memory at least a part of message data written into said data buffer from said information processing apparatus, and then executes the processing according to the message data.

12. A data processing apparatus according to claim 11, wherein said data processing circuit provides processing such that, when message data written into said data buffer from said information processing apparatus is encrypted message data, the encrypted message data is transferred to said local memory prior to decoding the encrypted message data into a plain text of message data.

13. A data processing apparatus according to claim 11, wherein said data processing circuit provides processing such that, when message data written into said data buffer from said information processing apparatus is message data with a signature, part of the message data with the signature except at least the signature is transferred to said local memory prior to a signature confirmation processing the message data.

14. A data processing apparatus comprising:

a data processing circuit performing decoding processing in which encrypted data is decoded, and message processing according to message data requesting the processing;

a data buffer connected to an external information processing apparatus, said data buffer being accessible from both said data processing circuit and said information processing apparatus;

a data buffer monitor circuit informing said data processing circuit, when a write-in of data from said information processing apparatus into said data buffer occurs, of the fact that the write-in of data has occurred, and informing said information processing apparatus, when a write-in of data from said data processing circuit into said data buffer occurs, of the fact that the write-in of data has occurred; and

an access control circuit controlling an access from said information processing apparatus to said data buffer,

wherein said data processing circuit performs a first processing of reading out encrypted data written into said data buffer from said information processing apparatus and writing the data thus read into said data buffer through practicing a decoding processing, a second processing of reading out message data written into said data buffer from said information processing apparatus and practicing a decoding processing to the message data thus read, and when executing the second processing, instructs said access control circuit to inhibit an access from said information processing apparatus to said data buffer.