PCI bus to IEEE 1394 bus translator
First Claim
1. A translator for interfacing between an IEEE 1394 bus and a Peripheral Component Interconnect (PCI) bus, wherein said translator is operable to allow a PCI device coupled to the PCI bus to communicate with an IEEE 1394 device coupled to the IEEE 1394 bus, comprising:
- a PCI slave coupled to the PCI bus, wherein said PCI slave is operable as a target of a PCI memory cycle initiated by the PCI device, wherein said PCI memory cycle includes an address;
an IEEE 1394 initiator coupled to said PCI slave operable to receive said PCI memory cycle address and translate said PCI memory cycle address into an IEEE 1394 address; and
packet dispatcher logic coupled to said IEEE 1394 initiator operable to receive said IEEE 1394 address and create an IEEE 1394 request packet including said IEEE 1394 address for transmission on the IEEE 1394 bus to the IEEE 1394 device;
packet receiver logic operable to receive an IEEE 1394 request packet from the IEEE 1394 device, wherein said request packet includes an IEEE 1394 address;
an IEEE 1394 slave coupled to said packet receiver logic operable to receive said IEEE 1394 address and translate said IEEE 1394 address into a PCI cycle address; and
a PCI master coupled to said IEEE 1394 slave operable to receive said PCI cycle address and initiate one or more PCI cycles on the PCI bus to the PCI device.
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Accused Products
Abstract
A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer. The translator, if configured to a first mode, pipelines subsequent PCI bus write cycles by posting the PCI write cycle data into the write-posting FIFO once reception of the first 1394 write request packet has been acknowledged by the host computer but prior to the host computer responding with status indicating the completion of the write transaction, in particular whether or not a resource conflict occurred. In response to a PCI read cycle initiated by the PCI device, the translator pre-fetches a larger amount of data than specified in the PCI read cycle from the host computer into a pre-fetch FIFO in order to satisfy subsequent PCI read cycles which are in address sequence with the previous PCI read cycle. The translator pre-fetches more data from the host computer once the pre-fetch FIFO becomes a predetermined amount empty in order to pipeline the consumption of the pre-fetch data by the PCI device and the transmission of the pre-fetch data by the host computer to the translator.
181 Citations
56 Claims
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1. A translator for interfacing between an IEEE 1394 bus and a Peripheral Component Interconnect (PCI) bus, wherein said translator is operable to allow a PCI device coupled to the PCI bus to communicate with an IEEE 1394 device coupled to the IEEE 1394 bus, comprising:
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a PCI slave coupled to the PCI bus, wherein said PCI slave is operable as a target of a PCI memory cycle initiated by the PCI device, wherein said PCI memory cycle includes an address; an IEEE 1394 initiator coupled to said PCI slave operable to receive said PCI memory cycle address and translate said PCI memory cycle address into an IEEE 1394 address; and packet dispatcher logic coupled to said IEEE 1394 initiator operable to receive said IEEE 1394 address and create an IEEE 1394 request packet including said IEEE 1394 address for transmission on the IEEE 1394 bus to the IEEE 1394 device; packet receiver logic operable to receive an IEEE 1394 request packet from the IEEE 1394 device, wherein said request packet includes an IEEE 1394 address; an IEEE 1394 slave coupled to said packet receiver logic operable to receive said IEEE 1394 address and translate said IEEE 1394 address into a PCI cycle address; and a PCI master coupled to said IEEE 1394 slave operable to receive said PCI cycle address and initiate one or more PCI cycles on the PCI bus to the PCI device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A translator for interfacing between an IEEE 1394 bus and a Peripheral Component Interconnect (PCI) bus, wherein said translator is operable to allow a PCI device coupled to the PCI bus to communicate with an IEEE 1394 device coupled to the IEEE 1394 bus, comprising:
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a PCI slave coupled to the PCI bus, wherein said PCI slave is operable as a target of a PCI memory cycle initiated by the PCI device, wherein said PCI memory cycle includes an address; an IEEE 1394 initiator coupled to said PCI slave operable to receive said PCI memory cycle address and translate said PCI memory cycle address into an IEEE 1394 address; and packet dispatcher logic coupled to said IEEE 1394 initiator operable to receive said IEEE 1394 address and create an IEEE 1394 request packet including said IEEE 1394 address for transmission on the IEEE 1394 bus to the IEEE 1394 device; wherein said PCI device comprises a PCI bus to VXI bus translator coupled to the PCI bus, wherein said PCI device further comprises a VXI instrument coupled to a VXI bus interface of said PCI bus to VXI bus translator.
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33. A translator for interfacing between an IEEE 1394 bus and a Peripheral Component Interconnect (PCI) bus, wherein said translator is operable to allow a PCI device coupled to the PCI bus to communicate with an IEEE 1394 device coupled to the IEEE 1394 bus, comprising:
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a PCI slave coupled to the PCI bus, wherein said PCI slave is operable as a target of a PCI memory cycle initiated by the PCI device, wherein said PCI memory cycle includes an address; an IEEE 1394 initiator coupled to said PCI slave operable to receive said PCI memory cycle address and translate said PCI memory cycle address into an IEEE 1394 address; and packet dispatcher logic coupled to said IEEE 1394 initiator operable to receive said IEEE 1394 address and create an IEEE 1394 request packet including said IEEE 1394 address for transmission on the IEEE 1394 bus to the IEEE 1394 device; wherein said PCI device comprises a PCI bus to GPIB bus translator coupled to the PCI bus, wherein said PCI device further comprises a GPIB instrument coupled to a GPIB bus interface of said PCI bus to GPIB bus translator.
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34. A system comprising:
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an IEEE 1394 device; an IEEE 1394 bus coupled to said IEEE 1394 device; a Peripheral Component Interconnect (PCI) device; a PCI bus coupled to said PCI device; and a translator for interfacing between said IEEE 1394 bus and said PCI bus, wherein said translator is operable to allow said PCI device coupled to said PCI bus to communicate with said IEEE 1394 device coupled to said IEEE 1394 bus, comprising; a PCI slave coupled to the PCI bus, wherein said PCI slave is operable as a target of a PCI memory cycle initiated by the PCI device, wherein said PCI memory cycle includes an address; an IEEE 1394 initiator coupled to said PCI slave operable to receive said PCI memory cycle address and translate said PCI memory cycle address into an IEEE 1394 address; and packet dispatcher logic coupled to said IEEE 1394 initiator operable to receive said IEEE 1394 address and create an IEEE 1394 request packet including said IEEE 1394 address for transmission on the IEEE 1394 bus to the IEEE 1394 device; packet receiver logic operable to receive an IEEE 1394 request packet from the IEEE 1394 device, wherein said request packet includes an IEEE 1394 address; an IEEE 1394 slave coupled to said packet receiver logic operable to receive said IEEE 1394 address and translate said IEEE 1394 address into a PCI cycle address; and a PCI master coupled to said IEEE 1394 slave operable to receive said PCI cycle address and initiate a PCI cycle on the PCI bus to the PCI device. - View Dependent Claims (35, 36, 37, 38, 39, 40)
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41. A system comprising:
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an IEEE 1394 device; an IEEE 1394 bus coupled to said IEEE 1394 device; a Peripheral Component Interconnect (PCI) bus; a PCI device coupled to said PCI bus, wherein said PCI device comprises a PCI bus to VXI bus translator including a PCI bus interface coupled to the PCI bus, wherein said PCI device further comprises a VXI instrument coupled to a VXI bus interface of said PCI bus to VXI bus translator; and translator for interfacing between said IEEE 1394 bus and said PCI bus, wherein said translator is operable to allow said PCI device coupled to said PCI bus to communicate with said IEEE 1394 device coupled to said IEEE 1394 bus, comprising; a PCI slave coupled to the PCI bus, wherein said PCI slave is operable as a target of a PCI memory cycle initiated by the PCI device, wherein said PCI memory cycle includes an address; an IEEE 1394 initiator coupled to said PCI slave operable to receive said PCI memory cycle address and translate said PCI memory cycle address into an IEEE 1394 address; and packet dispatcher logic coupled to said IEEE 1394 initiator operable to receive said IEEE 1394 address and create an IEEE 1394 request packet including said IEEE 1394 address for transmission on the IEEE 1394 bus to the IEEE 1394 device.
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42. A system comprising:
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an IEEE 1394 device; an IEEE 1394 bus coupled to said IEEE 1394 device; a Peripheral Component Interconnect (PCI) bus; a PCI device coupled to said PCI bus, wherein said PCI device comprises a PCI bus to GPIB bus translator including a PCI bus interface coupled to the PCI bus, wherein said PCI device further comprises a GPIB instrument coupled to a GPIB bus interface of said PCI bus to GPIB bus translator; and translator for interfacing between said IEEE 1394 bus and said PCI bus, wherein said translator is operable to allow said PCI device coupled to said PCI bus to communicate with said IEEE 1394 device coupled to said IEEE 1394 bus, comprising; a PCI slave coupled to the PCI bus, wherein said PCI slave is operable as a target of a PCI memory cycle initiated by the PCI device, wherein said PCI memory cycle includes an address; an IEEE 1394 initiator coupled to said PCI slave operable to receive said PCI memory cycle address and translate said PCI memory cycle address into an IEEE 1394 address; and packet dispatcher logic coupled to said IEEE 1394 initiator operable to receive said IEEE 1394 address and create an IEEE 1394 request packet including said IEEE 1394 address for transmission on the IEEE 1394 bus to the IEEE 1394 device.
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43. A method for translating memory cycles initiated on a PCI bus by a PCI device into one or more transactions with an IEEE 1394 device coupled to an IEEE 1394 bus, wherein the PCI bus memory cycles include a PCI memory cycle address, the method comprising:
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receiving a PCI bus memory cycle initiated by the PCI device; translating said PCI memory cycle address into an IEEE 1394 address; and creating an IEEE 1394 request packet including said IEEE 1394 address for transmission on the IEEE 1394 bus to the IEEE 1394 device; receiving an IEEE 1394 request packet from the IEEE 1394 device, wherein said request packet includes an IEEE 1394 address; translating said IEEE 1394 address into a PCI cycle address; and initiating a PCI cycle on the PCI bus to the PCI device, wherein said PCI cycle includes said translated PCI cycle address. - View Dependent Claims (44, 45, 46, 47)
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48. A system comprising:
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a host computer system including an IEEE 1394 bus interface; an IEEE 1394 bus cable coupled to said IEEE 1394 interface, wherein the IEEE 1394 bus cable implements an IEEE 1394 bus; and a remote Peripheral Component Interconnect (PCI) device coupled to the IEEE 1394 bus cable, wherein the remote PCI device includes; a PCI bus interface; and a translator coupled to said PCI bus interface and coupled to said IEEE 1394 bus cable for interfacing between said IEEE 1394 bus interface and said PCI bus interface, wherein said translator is operable to allow said remote PCI device to communicate with said IEEE 1394 bus, the translator comprising; a PCI slave coupled to the PCI bus interface, wherein said PCI slave is operable as a target of a PCI memory cycle initiated by the PCI device, wherein said PCI memory cycle includes an address; an IEEE 1394 initiator coupled to said PCI slave operable to receive said PCI memory cycle address and translate said PCI memory cycle address into an IEEE 1394 address; and packet dispatcher logic coupled to said IEEE 1394 initiator operable to receive said IEEE 1394 address and create an IEEE 1394 request packet including said IEEE 1394 address for transmission on the IEEE 1394 bus to the IEEE 1394 interface. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55)
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56. A system comprising:
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a host computer system including a memory-mapped serial bus interface; a serial bus cable coupled to said serial bus interface, wherein the serial bus cable implements a memory-mapped serial bus; and a remote input/output (I/O) device coupled to the serial bus cable, wherein the remote I/O device includes; an expansion bus interface; and a translator coupled to expansion bus interface and coupled to said serial cable for interfacing between said serial bus interface and said expansion bus interface, wherein said translator is operable to allow said remote I/O device to communicate with said serial bus, the translator comprising; an expansion bus slave coupled to the expansion bus interface, wherein said expansion bus slave is operable as a target of an expansion bus memory cycle initiated by the I/O device, wherein said expansion bus memory cycle includes an address; a serial bus initiator coupled to said expansion bus slave operable to receive said expansion bus memory cycle address and translate said expansion bus memory cycle address into a serial bus address; and packet dispatcher logic coupled to said serial bus initiator operable to receive said serial bus address and create a serial bus request packet including said serial bus address for transmission on the serial bus to the serial bus interface.
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Specification