Microprocessor circuits, systems, and methods implementing a loop and/or stride predicting load target buffer
First Claim
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1. A method of operating a microprocessor having an instruction pipeline, comprising the steps of:
- receiving a data fetching instruction in the instruction pipeline over a plurality of incidents, wherein each of the plurality of incidents produces a corresponding plurality of actual target data addresses for the data fetching instruction;
forming an entry in a load target buffer on the microprocessor in response to a first one of the plurality of incidents, wherein the entry corresponds to the data fetching instruction;
in response to the plurality of incidents, encoding in the entry a prediction of a target data address, wherein the prediction is based on the corresponding plurality of actual target data addresses for the data fetching instruction;
wherein the prediction is selected from a first prediction type and a second prediction type;
wherein the first prediction type is a loop mode such that the plurality of actual target data addresses form a loop sequence having a beginning loop target data address and passing to an ending loop target data address and repeating by returning to the beginning loop target data address; and
wherein the second prediction type is a stride mode such that the plurality of actual target data addresses pass from a beginning stride target data address and pass to a number of additional successive addresses, wherein the target data address of each of the successive target addresses has a common distance between itself and a target data address of an immediately preceding target data address.
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Abstract
A load target circuit (56) with a plurality of entries (561). Each the plurality of entries in the load target circuit comprises a value (ADDRESS TAG) for corresponding the line to a data fetching instruction. Additionally, each load target circuit line also includes a plurality of pointers (POINTER A, POINTER B, POINTER C). Each of the plurality of pointers is for storing a target data address corresponding to an incident of the data fetching instruction.
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Citations
17 Claims
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1. A method of operating a microprocessor having an instruction pipeline, comprising the steps of:
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receiving a data fetching instruction in the instruction pipeline over a plurality of incidents, wherein each of the plurality of incidents produces a corresponding plurality of actual target data addresses for the data fetching instruction; forming an entry in a load target buffer on the microprocessor in response to a first one of the plurality of incidents, wherein the entry corresponds to the data fetching instruction; in response to the plurality of incidents, encoding in the entry a prediction of a target data address, wherein the prediction is based on the corresponding plurality of actual target data addresses for the data fetching instruction; wherein the prediction is selected from a first prediction type and a second prediction type; wherein the first prediction type is a loop mode such that the plurality of actual target data addresses form a loop sequence having a beginning loop target data address and passing to an ending loop target data address and repeating by returning to the beginning loop target data address; and wherein the second prediction type is a stride mode such that the plurality of actual target data addresses pass from a beginning stride target data address and pass to a number of additional successive addresses, wherein the target data address of each of the successive target addresses has a common distance between itself and a target data address of an immediately preceding target data address.
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2. A load target circuit, comprising:
a plurality of entries, wherein each of the plurality of entries comprises; a value for corresponding the line to a data fetching instruction; and a plurality of pointers, wherein each of the plurality of pointers is for storing a target data address corresponding to an incident of the data fetching instruction, wherein each of the plurality of entries further comprises a next pointer value for identifying which one of the plurality of pointers provides the target data address for a given incident of the data fetching instruction. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
Specification