Active matrix panel manufacturing method including TFTS having variable impurity concentration levels

• US 5,953,582 A
• Filed: 06/27/1997
• Issued: 09/14/1999
• Est. Priority Date: 02/10/1993
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Yudasaka, Ichio, Matsuo, Minoru, Takenaka, Satoshi
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US08/999,540
• Time in Patent Office: 809 Days
• Field of Search: 438/154, 438/155, 438/163, 438/200, 438/29, 438/FOR 155, 438/FOR 184, 438/FOR 201, 438/FOR 168, 438/FOR 216, 438/FOR 217, 438/FOR 218
• US Class Current: 438/29
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

In the formation of a thin-film transistor (620) capable of improving the OFF current characteristic, first, all ions (arrow Ion-1) generated from a mixed gas (doping gas) containing 5% PH₃ with the remainder being H₂ gas are implanted to a polycrystalline silicon film (604) at an approximately 80 keV energy level to achieve a P⁺ ion dose in the range from 3×10¹³ /cm² to 1×10¹⁴ /cm² in the process forming low concentration source-drain areas (602, 603). Next, all ions generated from a doping gas of pure hydrogen (arrow Ion-2) are implanted to the low concentration area (604a) at an approximately 20 keV energy level to achieve an H⁺ ion dose from 1×10¹⁴ /cm² to 1×10¹⁵ /cm². Then, the impurity is activated by heat treatment of the low concentration area (604a) implanted with impurity for approximately one hour at approximately 300° C. in a nitrogen atmosphere.

Claims

1. A method for manufacturing an active matrix panel, comprising the steps of:

(A) patterning first and second silicon films on a surface of an insulated substrate to form first and second thin film transistors of a CMOS drive circuit;

(B) patterning a third silicon film on the surface of the insulated substrate to form a third thin film transistor for a pixel within a pixel matrix disposed on the insulated substrate surface;

(C) forming a gate insulating film on an exposed surface of each of the first, second and third silicon films;

(D) forming a gate electrode on a portion of each gate insulating film;

(E) implanting the first, second and third silicon films with impurities of a first conductivity type;

(F) masking the first and third silicon films with a first mask;

(G) implanting the second silicon film with impurities of a second conductivity type using the gate electrode of the second thin film transistor as a second mask;

(H) removing the first mask;

(I) masking the second silicon film, the third gate electrode and a portion of the third silicon film with a third mask leaving at least one portion of the third silicon film unmasked;

(J) implanting the first silicon film and the unmasked portion of the third silicon film with impurities of the first conductivity type using the gate electrode of the first thin film transistor as a fourth mask to provide the third thin film transistor with a lightly doped drain structure;

(K) removing the third mask,

(L) forming a layer insulation film on at least the third silicon film and the gate electrode therefor, the layer of insulation film having at least one contact hole formed therein; and

(M) forming an electrode on at least a portion of the layer insulation film such that the electrode is connected to the at least one unmasked portion of the third silicon film through the at least one contact hole.

2. The method of claim 1, wherein said implanting step (E) comprises implanting the first, second and third silicon films with impurities of the first conductivity type at a dose not exceeding 1×

10¹⁴ /cm².

3. The method of claim 1, wherein said implanting step (G) comprises implanting the second silicon film with impurities of the second conductivity type at a dose exceeding 1×

10¹⁴ /cm².

4. The method of claim 2, wherein said implanting step (G) comprises implanting the second silicon film with impurities of the second conductivity type at a dose exceeding 1×

10¹⁴ /cm².

5. The method of claim 1, wherein, in said masking step (I), the at least one unmasked portion includes a portion of a source area and a portion of a drain area of the third thin film transistor;

and wherein, in said layer insulation film forming step (L), the at least one contact hole includes a first contact hole corresponding to the portion of the source area and a second contact hole corresponding to the portion of the drain area.

6. The method of claim 1, wherein said implanting step (E) further comprises forming a low concentration area in each of the first, second and third silicon films;

and wherein said implanting step (J) further comprises forming high concentration areas in the third silicon film.