Method of manufacturing thin film transistor

• US 5,953,595 A
• Filed: 09/27/1996
• Issued: 09/14/1999
• Est. Priority Date: 09/29/1995
• Status: Expired due to Term

• Current Assignee: Japan Display West Incorporated (Japan Display Incorporated)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Gosain, Dharam Pal, Usui, Setsuo, Nakagoe, Miyako, Westwater, Jonathan
• Primary Examiner(s): Brown, Peter Toby
• Assistant Examiner(s): DUONG, KHANH B
• Application Number:
  US08/721,948
• Time in Patent Office: 1,082 Days
• Field of Search: 438/158, 438/162, 438/166, 438/301, 438/487, 438/753, 438/949
• US Class Current: 438/158
• CPC Class Codes: G03F 7/42 Stripping or agents therefor
• CPC Class Codes: H01L 21/02046 Dry cleaning only H01L21/02085 takes precedence
• CPC Class Codes: H01L 21/0272 for lift-off processes
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: Y10S 438/949 Energy beam treating radiation resist on semiconductor

Abstract

The manufacturing processes can be simplified and the reliability can be improved. A method of processing a thin film includes a first process of selectively forming a resist pattern on a ground surface, a second process of forming a thin film on the ground surface and a surface of the resist pattern, and a third process of removing the resist pattern to selectively remove the thin film deposited on the former, i.e., carrying out the lift-off, thereby the thin film process for a desired pattern being carried out.

Claims

1. A method for making a thin film semiconductor device comprising the steps of:

providing a transparent substrate having an upper surface and an opposed lower surface;

forming a gate electrode on the upper surface having a width dimension;

forming an impurity shielding layer on the upper surface and exposed upper surface of the gate electrode;

forming a gate insulating film on the impurity shielding layer;

applying a photoresist layer on said gate insulating film;

exposing the substrate from the lower surface side to light to develop exposed portions of the photoresist layer;

removing exposed portions of the resist layer to provide a remaining unexposed resist portion above the gate electrode, said resist portion having a first width substantially equal to the width of the gate electrode;

heating and flowing the resist portion to provide a deformed resist portion having a second width greater than said first width;

forming a relatively higher concentration impurity containing first amorphous silicon layer on said deformed resist portion and adjacent portions of said gate insulating film;

removing the deformed resist portion and any overlying portions of the first impurity containing amorphous silicon layer to provide first and second separated portions of the impurity containing first amorphous silicon layer on opposed sides of the gate electrode and spaced from the gate electrode by an offset width;

forming a relatively lower concentration impurity containing second amorphous silicon layer on said first and second portions and exposed portions of said gate insulating film;

laser annealing to diffuse and activate impurities in said first and second amorphous silicon layers to define source and drain regions on opposite sides of the gate electrode and spaced from the gate electrode by an offset width; and

thereafter, forming source and drain electrodes disposed in ohmic contact with said source and drain regions, respectively.

2. A method as defined in claim 1, further comprising the step of subjecting the second amorphous silicon layer to hydrogen plasma processing followed by a second laser annealing before forming said source and drain electrodes.

3. A method as defined in claim 2, further comprising the step of forming a SiN layer on the second amorphous silicon layer prior to hydrogen plasma processing and wherein the source and drain electrodes extend through openings formed in the SiN layer to make ohmic contact with the source and drain regions.

4. A method as defined in claim 1, wherein said transparent substrate comprises glass, quartz or plastic.

5. A method as defined in claim 1, wherein said gate electrode comprises a metal selected from the group consisting of Al, Mo and Ti.

6. A method as defined in claim 1, wherein said impurity shielding layer comprises SiN.

7. A method as defined in claim 1, wherein said gate insulating film comprises SiO₂.

8. A method as defined in claim 1, wherein said photoresist comprises an organic positive photoresist.

9. A method as defined in claim 1, wherein in the step of heating and flowing the resist portion to provide the deformed resist portion, the resist portion is heated at a temperature of about 140°

C.

10. A method as defined in claim 1, wherein said first amorphous silicon layer is formed by plasma enhanced chemical vapor deposition at a temperature less than about 150°

C.

11. A method as defined in claim 1, wherein the step of removing the deformed resist is performed by a wet process employing super ultrasonic vibration and acetone.