EEPROM cell and related method of making thereof

• US 5,953,602 A
• Filed: 11/25/1997
• Issued: 09/14/1999
• Est. Priority Date: 05/26/1995
• Status: Expired due to Term

• Current Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Original Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Inventors: Kim, Jang Han, Oh, Han Su
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LATTIN, CHRISTOPHER W
• Application Number:
  US08/978,028
• Time in Patent Office: 658 Days
• Field of Search: 438/201, 438/257, 438/259, 438/264
• US Class Current: 438/201
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

An EEPROM cell of reduced leakage current during erasure and improved cell topology includes a first conductivity type substrate having a channel region, a trench formed in the channel region of the substrate, first spacers formed on opposed sidewalls of the trench, and a gate oxide film formed at the bottom of the trench between the first spacers. Second conductivity type source/drain regions are formed in the substrate at opposite side of the trench. A tunneling oxide film is further provided on the substrate overlying the drain region and proximate the trench. An insulation film is provided over the entire substrate surface except the trench and the tunneling oxide film. In addition, a floating gate is formed on the insulation film over the source and drain regions, as well as the gate oxide film at the trench bottom. Second spacers are provided on the insulation film at opposed side surfaces of the floating gate. A dielectric film is then provided on the surface of the floating gate and the second spacers, and a control gate is formed on the dielectric film.

Claims

1. The method for fabricating an EEPROM cell comprising the steps of:

forming a first insulation film on a semiconductor substrate having a first conductivity type and a surface;

forming a first photoresist film on said first insulation film;

patterning said first photoresist film to expose first and second portions of said first insulation film by a photoetching process;

forming a source region having a second conductivity type by implanting impurities into said substrate through said exposed first portion of said first insulation film using said first photoresist film as a mask, said source region having a predetermined junction depth;

forming a drain region having said second conductivity type by implanting impurities into said substrate through said exposed second portion of said first insulation film using said first photoresist film as said mask, said drain region having said predetermined junction depth;

forming a trench by etching said substrate between source and drain regions and etching portions of said source and drain region;

forming first and second spacers on sidewalls of said trench by coating a second insulation film over said surface of said substrate and anisotropically etching said second insulation film, said first spacer being adjacent said drain region and said second spacer is adjacent said source region;

forming a gate oxide film on a bottom of said trench between said first and second spacers;

forming a tunneling oxide film over said drain region adjacent said first spacer;

forming a floating gate on said first insulation film overlying said source and drain region, said floating gate being formed on said tunneling oxide film and in said trench, said step of forming said floating gate including the steps of coating a film on said surface of substrate and patterning said film;

forming third and fourth spacers on said first insulation film at side surfaces, of said floating gate by providing a third insulation film on said surface of said substrate and anisotropically etching said third insulation film;

forming a capacitor dielectric film on said floating gate and said third and fourth spacers; and

forming a control gate on said dielectric film.

2. The method for fabricating an EEPROM cell in accordance with claim 1, wherein junction depths of said source and drain regions are deeper than a depth of said trench.

3. The method for fabricating an EEPROM cell in accordance with claim 1, further comprising a step of implanting impurities into said substrate to adjust a threshold voltage of said EEPROM cell.

4. The method for fabricating an EEPROM cell in accordance with claim 1, wherein said first insulation film includes an oxide film.

5. The method for fabricating an EEPROM cell in accordance with claim 1, wherein said step of forming said tunneling oxide film further comprises the steps of:

coating a second photoresist film over said surface of said substrate;

selectively removing portions of said second photoresist film to expose a portion of said first insulation film overlying said drain region adjacent said first spacer;

removing said exposed portion of said first insulation film using said second photoresist film as a mask to expose a portion of said surface of said substrate overlying said drain region;

forming a tunneling oxide film on said exposed portion of said substrate surface by an oxidation process, said tunneling oxide being formed over said drain region.