Method for fabricating semiconductor wafers

• US 5,953,622 A
• Filed: 09/15/1997
• Issued: 09/14/1999
• Est. Priority Date: 11/23/1996
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Park, Sang Kyun, Lee, Sahng Kyoo
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US08/929,793
• Time in Patent Office: 729 Days
• Field of Search: 438/406, 438/458, 438/FOR 222, 438/FOR 64, 148/DIG. 12
• US Class Current: 438/458
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

A method for fabricating silicon-on-insulator (SOI) wafers which is capable of simplifying the fabrication process while improving the productivity of SOI wafers. In accordance with this method, a first wafer formed with a thermal oxide film is bonded to a second wafer formed with an oxygen ion-implanted region and a hydrogen ion-implanted region. The bonded wafer structure is annealed and then cut along the hydrogen ion-implanted region, so that it is divided into two wafer structures. The wafer structure including the first wafer is annealed to obtain a strengthened chemical coupling property. The wafer structure including the second wafer is annealed to oxidize the oxygen ion-implanted region of the second wafer, thereby forming an oxide film in the second wafer. The first and second wafers are then planarized, thereby forming a pair of SOI wafers.

Claims

1. A method for fabricating semiconductor wafers, comprising the steps of:

providing a first wafer and a second wafer;

forming a thermal oxide film over the first wafer;

implanting oxygen ions in the second wafer, thereby forming an oxygen ion-implanted region;

implanting hydrogen ions in the second wafer, thereby forming a hydrogen ion-implanted region shallower than the oxygen ion-implanted region;

bonding the upper surface of the second wafer to the upper surface of the thermal oxide film formed over the first wafer;

annealing the bonded wafers;

cutting the bonded wafers along the hydrogen ion-implanted region, thereby forming a first silicon-on-insulator (SOI) wafer and a bare wafer;

annealing the first SOI wafer, thereby strengthening a chemical coupling property of the first SOI wafer;

annealing the bare wafer in such a manner that the oxygen ion-implanted region included in the bare wafer is oxidized, thereby forming a second SOI wafer; and

planarizing the surfaces of the first and second SOI wafers.

2. The method in accordance with claim 1, wherein the formation of the thermal oxide film is carried out by annealing the first wafer at a temperature of about 900 to 1,100°

C. for about 30 to 60 minutes.

3. The method in accordance with claim 1, wherein the formation of the thermal oxide film has a thickness of about 500 to 10,000 Å

.

4. The method in accordance with claim 1, wherein the formation of the hydrogen ion-implanted region is carried out using ion implantation energy of 10 KeV to 2 MeV.

5. The method in accordance with claim 1, wherein the formation of the hydrogen ion-implanted region is carried out using a dose of 1×

10¹⁶ /cm² to 1×

10¹⁷ /cm².

6. The method in accordance with claim 1, wherein the formation of the oxygen ion-implanted region is carried out using ion implantation energy of 10 KeV to 2 MeV.

7. The method in accordance with claim 1, wherein the formation of the oxygen ion-implanted region is carried out using a dose of 1×

10¹² /cm² to 1×

10¹⁶ /cm².

8. The method in accordance with claim 1, wherein the annealing of the bonded wafers is carried out at a temperature of about 400 to 600°

C.

9. The method in accordance with claim 1, wherein the annealing of the first SOI wafer is carried out at a temperature of about 900 to 1,200°

C.

10. The method in accordance with claim 1, wherein the annealing of the second SOI wafer is carried out at a temperature of 900 to 1,200°

C. for about 30 to 100 minutes in a nitrogen or oxygen atmosphere.

11. The method in accordance with claim 1, wherein the planarizing step is carried out using a chemical mechanical polishing method.

12. The method in accordance with claim 1, wherein the planarizing step is carried out under the condition using a table speed ranging from 15 rpm to 40 rpm, a back pressure of the polishing head ranging less than 2 psi, and a wafer-depressing pressure of the polishing head ranging less than 9 psi, while using a KOH or NH₄ OH-based slurry.

13. A method for fabricating semiconductor wafers, comprising the steps of:

providing a first wafer and a second wafer;

forming a first thermal oxide film over the first wafer;

forming a second thermal oxide film over the second wafer;

sequentially implanting oxygen ions and hydrogen ions in the second wafer, thereby forming an oxygen ion-implanted region and a hydrogen ion-implanted region;

bonding the upper surface of the second wafer to the upper surface of the first wafer;

annealing the bonded wafers;

cutting the bonded wafers along the hydrogen ion-implanted region, thereby forming a first silicon-on-insulator (SOI) wafer and a bare wafer;

annealing the first SOI wafer, thereby strengthening a chemical coupling property of the first SOI wafer;

annealing the bare wafer in such a manner that the oxygen ion-implanted region included in the bare wafer is oxidized, thereby forming a second SOI wafer; and

planarizing the surfaces of the first and second SOI wafers.

14. The method in accordance with claim 13, wherein the thermal oxide films are formed to a thickness of about 500 to 10,000 Å

by annealing the associated wafers at a temperature of about 900 to 1,100°

C. for about 30 to 60 minutes.

15. The method in accordance with claim 13, wherein the formation of the hydrogen ion-implanted region is carried out using ion implantation energy of 10 KeV to 2 MeV and a dose of 1×

10¹⁶ /cm² to 1×

10¹⁷ /cm².

16. The method in accordance with claim 13, wherein the formation of the oxygen ion-implanted region is carried out using ion implantation energy of 10 KeV to 2 MeV and a dose of 1×

10¹² /cm² to 1×

10¹⁶ /cm².

17. The method in accordance with claim 13, wherein the annealing of the bonded wafers is carried out at a temperature of about 400 to 600°

C.

18. The method in accordance with claim 13, wherein the annealing of the first SOI wafer is carried out at a temperature of about 900 to 1,200°

C.

19. The method in accordance with claim 13, wherein the annealing of the second SOI wafer is carried out at a temperature of 900 to 1,200°

C. for about 30 to 100 minutes in a nitrogen or oxygen atmosphere.

20. The method in accordance with claim 13, wherein the planarizing step is carried out in accordance with a chemical mechanical polishing method under the condition using a table speed ranging from 15 rpm to 40 rpm, a back pressure of the polishing head ranging less than 2 psi, and a wafer-depressing pressure of the polishing head ranging less than 9 psi, while using a KOH or NH₄ OH-based slurry.