Dissolvable dielectric method

• US 5,953,626 A
• Filed: 06/05/1996
• Issued: 09/14/1999
• Est. Priority Date: 06/05/1996
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dawson, Robert, Michael, Mark W., Brennan, William S., Fulford, H. Jim Jr., Bandyopadhyay, Basab, Hause, Fred N.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Berry, Renee R.
• Application Number:
  US08/659,166
• Time in Patent Office: 1,196 Days
• Field of Search: 438/152, 438/158, 438/207, 438/210, 438/234, 438/593, 438/622, 438/637, 438/692
• US Class Current: 438/622
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps

Abstract

A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.

Claims

1. A method of fabricating interconnect levels on a semiconductor substrate comprising:

forming a barrier layer on said substrate;

forming a first interconnect level on said barrier layer wherein said first interconnect level comprises a plurality of substantially coplanar first conductors;

forming a first temporary support material on said first interconnect level, said first temporary support material comprising an upper surface and a lower surface;

forming a plurality of vias in said first temporary support material, said plurality of vias extending from said upper surface of said first temporary support material to said lower surface of said first temporary support material and wherein at least one of said plurality of vias communicates with one or more of said first conductors;

filling said plurality of vias with a conductive material to form a plurality of permanent support pillars having an upper end substantially coplanar with said upper surface of said first temporary support material, wherein at least one of said permanent support pillars contacts at least one of said plurality of first conductors;

forming a second temporary support material and a second interconnect level on said first temporary support layer wherein said second interconnect level comprises a plurality of substantially coplanar second conductors spaced apart by said second temporary support material; and

concurrently removing said first and second temporary support materials from said first and second interconnect levels such that said plurality of second conductors are separated from said first conductors by air and wherein said second conductors are supported above said plurality of first conductors by said plurality of permanent conductive pillars.

2. The method of claim 1 wherein said barrier layer comprises silicon nitride.

3. The method of claim 1 wherein said barrier layer comprises undoped polysilicon.

4. The method of claim 1 wherein said barrier layer comprises metal oxide.

5. The method of claim 1 wherein the step of forming said first interconnect level comprises depositing a conductive material on said barrier layer, patterning a photoresist layer on said conductive material, and etching said conductive material to produce said plurality of substantially coplanar first conductors.

6. The method of claim 5 wherein said conductive material comprises aluminum, copper, or tungsten.

7. The method of claim 1 wherein said conductive material comprises aluminum, copper, or tungsten.

8. The method of claim 1 wherein said temporary material comprises oxide formed from a chemical vapor deposition process using a TEOS or silane source.

9. The method of claim 1 wherein said forming a second temporary support material and a second interconnect level comprises depositing said temporary support material on said first temporary support material, etching a plurality of second trenches into said second temporary support material, depositing a conductive material in said plurality of second trenches, and polishing back said conductive material to produce said plurality of substantially coplanar second conductors.

10. The method of claim 1 wherein the step of forming said second interconnect level comprises depositing a conductive material on said first temporary support layer, patterning a photoresist layer on said conductive material, and etching said conductive material to produce said plurality of substantially coplanar first conductors.

11. The method of claim 1 further comprising:

depositing a passivation layer on said second interconnect level; and

etching a plurality of vias through said passivation layer wherein said passivation layer vias are horizontally displaced from said second conductors.

12. The method of claim 11 further comprising depositing a capping dielectric layer on said passivation layer.