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Single-chip DBS receiver

  • US 5,953,636 A
  • Filed: 10/30/1996
  • Issued: 09/14/1999
  • Est. Priority Date: 10/30/1996
  • Status: Expired due to Term
First Claim
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1. A DBS receiver system comprising:

  • a tuner configured to receive a high frequency signal;

    an analog to digital converter operatively coupled to said tuner; and

    a receiver chip coupled to receive a digital signal from said analog to digital converter, said receiver chip comprising;

    a demodulator stage configured to receive said digital signal;

    a convolutional decoder stage operatively coupled to said demodulator stage; and

    a de-interleaver and block decoder stage operatively coupled to said convolutional decoder stage;

    wherein said demodulator stage includes;

    a matched filter configured to receive said digital signal;

    a module for clock synchronization, carrier synchronization and gain control, coupled to said matched filter; and

    a module for providing a first feedback signal coupled to said analog to digital converter to provide clock synchronization;

    wherein said first feedback signal module includes;

    a crystal oscillator configured to provide a high frequency clock reference signal;

    a loop filter coupled to receive an error signal and adjust a voltage signal which said loop filter provides;

    a voltage controlled oscillator coupled to receive said voltage signal and provide a clock signal with a clock rate substantially proportional to said voltage signal; and

    an automated frequency controller configured to receive a digital signal representing a desired clock rate, said automated frequency controller also being coupled to receive said high frequency clock reference signal and said clock signal, said automated frequency controller configured to provide said error signal indicating that said clock rate is higher than desired clock rate or lower than desired clock rate.

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