Single-chip DBS receiver
First Claim
Patent Images
1. A DBS receiver system comprising:
- a tuner configured to receive a high frequency signal;
an analog to digital converter operatively coupled to said tuner; and
a receiver chip coupled to receive a digital signal from said analog to digital converter, said receiver chip comprising;
a demodulator stage configured to receive said digital signal;
a convolutional decoder stage operatively coupled to said demodulator stage; and
a de-interleaver and block decoder stage operatively coupled to said convolutional decoder stage;
wherein said demodulator stage includes;
a matched filter configured to receive said digital signal;
a module for clock synchronization, carrier synchronization and gain control, coupled to said matched filter; and
a module for providing a first feedback signal coupled to said analog to digital converter to provide clock synchronization;
wherein said first feedback signal module includes;
a crystal oscillator configured to provide a high frequency clock reference signal;
a loop filter coupled to receive an error signal and adjust a voltage signal which said loop filter provides;
a voltage controlled oscillator coupled to receive said voltage signal and provide a clock signal with a clock rate substantially proportional to said voltage signal; and
an automated frequency controller configured to receive a digital signal representing a desired clock rate, said automated frequency controller also being coupled to receive said high frequency clock reference signal and said clock signal, said automated frequency controller configured to provide said error signal indicating that said clock rate is higher than desired clock rate or lower than desired clock rate.
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Abstract
The present invention concerns a DBS receiver which serves to combine the functions of variable rate demodulation, convolutional decoding, de-interleaving and block decoding. The demodulation stage includes a novel circuit for clock synchronization. By combining the functions of these components this device provides a higher level of utility as measured in terms of reliability, simplicity, flexibility, cost effectiveness, and integration of board layout while maintaining optimum-quality signal processing.
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Citations
15 Claims
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1. A DBS receiver system comprising:
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a tuner configured to receive a high frequency signal; an analog to digital converter operatively coupled to said tuner; and a receiver chip coupled to receive a digital signal from said analog to digital converter, said receiver chip comprising; a demodulator stage configured to receive said digital signal; a convolutional decoder stage operatively coupled to said demodulator stage; and a de-interleaver and block decoder stage operatively coupled to said convolutional decoder stage; wherein said demodulator stage includes; a matched filter configured to receive said digital signal; a module for clock synchronization, carrier synchronization and gain control, coupled to said matched filter; and a module for providing a first feedback signal coupled to said analog to digital converter to provide clock synchronization; wherein said first feedback signal module includes; a crystal oscillator configured to provide a high frequency clock reference signal; a loop filter coupled to receive an error signal and adjust a voltage signal which said loop filter provides; a voltage controlled oscillator coupled to receive said voltage signal and provide a clock signal with a clock rate substantially proportional to said voltage signal; and an automated frequency controller configured to receive a digital signal representing a desired clock rate, said automated frequency controller also being coupled to receive said high frequency clock reference signal and said clock signal, said automated frequency controller configured to provide said error signal indicating that said clock rate is higher than desired clock rate or lower than desired clock rate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A DBS receiver system comprising:
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a tuner configured to receive a high frequency signal; an analog to digital converter operatively coupled to said tuner; a receiver chip coupled to receive a digital signal from said analog to digital converter, said receiver chip coupled to a crystal oscillator to receive a high frequency clock reference signal, said receiver chip also coupled to a loop filter to provide an error signal; and a voltage controlled oscillator coupled to receive a voltage signal from said loop filter and configured to provide a clock signal with a clock rate substantially proportional to said voltage signal; wherein said receiver chip includes an automated frequency controller configured to receive a digital signal representing a desired clock rate, said automated frequency controller also being coupled to receive said high frequency clock reference signal and said clock signal, said automated frequency controller configured to provide said error signal indicating that said clock rate is higher than desired clock rate or lower than desired clock rate, said automated frequency controller comprising; a first counter configured to count for a configurable time interval based on output of said crystal oscillator; and a second counter configured to count a number of clock cycles in the clock signal during said time interval. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification