System and method for estimating clock error in a remote communication device

• US 5,953,648 A
• Filed: 08/13/1996
• Issued: 09/14/1999
• Est. Priority Date: 08/13/1996
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Hutchison, James A. IV, Hughes, Robbin D.
• Primary Examiner(s): Le, Vu
• Application Number:
  US08/696,288
• Time in Patent Office: 1,127 Days
• Field of Search: 455/343, 455/68, 455/69, 455/502-503, 455/550, 455/180.3, 455/13.2, 455/260, 455/226.1, 455/192.1-192.3, 455/574, 455/38.3, 455/75-76, 455/71, 375/359, 375/293-294, 375/226, 375/354, 375/363-364
• US Class Current: 455/343.4
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04W 52/0258 controlling an operation mode according to history or models of usage information, e.g. activity schedule or time of day
• CPC Class Codes: H04W 52/0261 managing power supply demand, e.g. depending on battery level
• CPC Class Codes: H04W 56/0035 detecting errors in frequency or phase
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

In a mobile telephone that includes an internal voltage controlled crystal oscillator clock, a clock error compensation system is provided that dynamically determines and compensates for clock error during periods in which the mobile telephone is asleep. The system drives the control voltage of the clock to one of the clock'"'"'s voltage limits, at which limit the sleep error of the clock can be expected to occur. This expected sleep error is then added to the number of clocking pulses which, in the absence of any clock error, would correspond to the length of the desired sleep period, to generate a corrected internal time. At the end of the sleep period as determined by the corrected internal time, the mobile telephone reacquires a system timing signal that represents actual system time, and the corrected internal time is then compared to the system time. The difference between corrected internal time and actual system time is added to the expected sleep error for the next sleep cycle, with succeeding sleep cycles being progressively longer as the expected sleep error of the clock is recursively determined and applied to the output of the internal clock.

Claims

1. A method for modifying the internal clock time of a mobile telephone including an internal voltage controlled clock characterized by an operating voltage and a rail voltage, the clock generating a sequence of output clocking pulses, comprising the steps of:

(a) receiving a desired sleep period corresponding to a first number of clocking pulses;

(b) defining an expected sleep error corresponding to the rail voltage;

(c) inputting the rail voltage to the clock, the rail voltage being a constant voltage at an input limit voltage of the clock; and

(d) adding the expected sleep error to the first number of clocking pulses to generate a corrected internal time.

2. The method of claim 1, further comprising the step of (e) partially powering down the telephone for the sleep period, the inputting step being accomplished at the start of the sleep period.

3. The method of claim 2, further comprising the step of (f) inputting the operating voltage to the clock in accordance with the corrected internal time.

4. The method of claim 3, further comprising the steps of:

(g) providing a system time;

(h) determining a difference between the system time and the corrected internal time; and

(i) modifying the expected sleep error in accordance with the difference.

5. The method of claim 4, further comprising the steps of:

(j) increasing the sleep period and the first number of pulses in proportion associated therewith after step (i), and

(k) repeating steps (c)-(i).

6. The method of claim 5, further comprising repeating steps (j) and (k).

7. An apparatus for determining an internal time in a mobile telephone in a telephone system, the telephone system defining a system time, the apparatus comprising:

a clock for generating an output signal representative of time in response to an input voltage, the output signal being characterized by a sequence of clocking pulses;

a sleep period definer, coupled to said clock, for defining a desired sleep period, the desired sleep period defining a number of clocking pulses;

an input voltage source controller, coupled to the clock, for establishing the input voltage to be a rail voltage at the start of the sleep period and for establishing the input voltage to be an operating voltage at the end of the sleep period, the rail voltage being a constant voltage at an input limit voltage of the clock, the clock exhibiting an expected sleep error at the rail voltage during the sleep period; and

a signal combiner associated with the clock and the sleep period definer for combining the expected sleep error with the number of clocking pulses to generate a corrected internal time.

8. The apparatus of claim 7, wherein the end of the sleep period is determined in accordance with the corrected internal time.

9. The apparatus of claim 7, further comprising a difference determiner for receiving a system time and a corresponding corrected internal time and determining the difference therebetween.

10. The apparatus of claim 9, further comprising a corrector for modifying the expected sleep error in accordance with the difference.

11. The apparatus of claim 10, wherein the sleep period definer doubles the sleep period after the corrector modifies the expected sleep error.

12. A digital processing apparatus comprising:

logic means for defining a desired sleep period of a mobile telephone in a telephone system implementing slotted paging, the desired sleep period defining a number of clocking pulses;

logic means for establishing an input voltage of a clock internal to the mobile telephone to be a rail voltage at the start of the sleep period and for establishing the input voltage to be an operating voltage at the end of the sleep period, the rail voltage being a constant voltage at an input limit voltage of the clock, the clock exhibiting an expected sleep error at the rail voltage during the sleep period; and

logic means for combining the expected sleep error with the number of clocking pulses to generate a corrected internal time.

13. The apparatus of claim 12, further comprising:

logic means for receiving a system time and a corrected internal time and determining the difference therebetween; and

logic means for modifying the expected sleep error in accordance with the difference.