DRAM with integral SRAM and arithmetic-logic units

• US 5,953,738 A
• Filed: 07/02/1997
• Issued: 09/14/1999
• Est. Priority Date: 07/02/1997
• Status: Expired due to Term

• Current Assignee: Foothills IP LLC
• Original Assignee: Silicon Aquarius Incorporated (NewMarket Technology, Inc.)
• Inventors: Rao, G. R. Mohan
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): GOODARZI, NASSER MOAZZAMI
• Application Number:
  US08/886,952
• Time in Patent Office: 804 Days
• Field of Search: 711/105, 711/5, 711/114, 365/230.03, 365/189.04, 364/900, 364/760.01
• US Class Current: 711/105
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Memory 400 is fabricated as a single integrated circuit chip and includes an array 402 of memory cells and circuitry 404/405/413 for accessing selected memory cells in array 402. At least one local ALU 414 is included for receiving data accessed from selected cells of array 402 and performing a selected operation thereon.

Claims

1. A memory fabricated as a single integrated circuit chip comprising:

an array of memory cells;

accessing circuitry for accessing selected memory cells of said array;

at least one local ALU for receiving data accessed from selected cells of said array and performing a selected operation thereon;

a register comprising a plurality of memory cells and coupled to said plurality of ALUs; and

second assessing circuitry for selectively accessing said cells of said register and presenting data accessed from selected ones of said cells to said plurality of ALUs wherein said second accessing circuitry compares a received address bit with a stored address bit and accesses said register when said received address bit matches said stored address bit.

2. The memory of claim 1 wherein each said ALU comprises an input for receiving an operand from a bus, said ALU performing said selected operation on said accessed data using said operand.

3. The memory of claim 1 wherein said at least one ALU comprises a plurality of parallel ALUs each for selectively operating on a portion of said accessed data.

4. The memory of claim 1 wherein said local ALU comprises a 4-bit ALU.

5. The memory of claim 3 wherein said array comprises N number of columns of cells each accessible by said accessing circuitry in response to a column address, selected ones of said ALUs operating on data accessed from an addressed said column of cells.

6. The memory of claim 5 wherein a said column comprises M number of bitlines partitioned into P number of subsets, each said subset coupled to a corresponding one of said plurality of ALUs.

7. The memory of claim 1 wherein said array comprises an array of dynamic random access memory cells.

8. The memory of claim 1 wherein said array comprises an array of static random access memory cells.

9. The memory of claim 1 wherein said at least one ALU comprises a plurality of local ALUs and said memory further comprises a global ALU for performing operations on results output from said plurality of local ALUs.

10. The memory of claim 1 wherein said register comprises an array of static random access memory cells.

11. A memory subsystem comprising:

an array of dynamic random access memory cells;

an array of static random access memory cells;

circuitry for accessing a cell of a selected one of said arrays in response to a received address bit;

an arithmetic logic unit for receiving data from said accessed cell and selectively performing an operation thereon wherein said circuitry for accessing is operable to compare a received address bit with a stored address bit and select a one of said arrays for access in response.

12. The memory of claim 11 wherein said memory subsystem is fabricated on a single integrated circuit chip.

13. The memory of claim 11 wherein said arithmetic logic unit further comprises an input for receiving an operand, said arithmetic operation in response performing said operation on said data using said operand.

14. The memory of claim 11 wherein said arithmetic logic unit comprises a results output coupled to a port of said memory subsystem.

15. The memory of claim 11 wherein said arithmetic logic unit comprises a carry output coupled to a port of said memory subsystem.

16. The memory of claim 11 wherein said circuitry for accessing selects said array of static random access memory cells when said received address bit and said stored address bit match.

17. The memory of claim 11 and further comprising a second arithmetic logic unit for selectively performing an operation on a result output from said arithmetic logic unit.

18. A memory comprising:

an array of dynamic random access memory cells;

an operand register for storing a received operand for selective use in an arithmetic-logic operation;

a result register for storing a result from an arithmetic logic operation;

an arithmetic logic unit for selectively performing an operation on data retrieved from said array of dynamic random access memory cells and an operand retrieved from said operand register, a result of said operation output by said arithmetic logic unit for selective storage in said result register wherein said circuitry for accessing is operable to compare a received address bit with a stored address bit and select at one of said arrays for access in response.

19. The memory of claim 18 wherein said results register comprises an array of static random access memory cells.

20. The memory of claim 18 wherein said operands register comprises and array of static random access memory.

21. A method of operating a single-chip memory including an array of dynamic random access memory cells, an array of static random access memory cells, circuitry for accessing a storage location of a selected one of the arrays, and an arithmetic logic unit, the method comprising the steps of:

selecting a one of the dynamic and static random cell arrays for access in response to a received address bit;

accessing a location in the selected one of the memory array;

performing an arithmetic logic operation on data from the accessed location using the arithmetic logic unit wherein said step of selecting comprises the substeps of;

comparing the received address bit with a prestored address bit; and

selecting the static array for access when the received address bit and the prestored address bit match and selecting the dynamic array for access when the received address bit and the prestored address bit do not match.

22. The method of claim 21 and further comprising the step of presenting result bits output from the arithmetic logic unit at an output port of the memory via a bus.

23. The method of claim 21 and further comprising the step of writing result bits output from the arithmetic logic unit into a selected one of the arrays.

24. The method of claim 21 wherein said step of performing an operation on the accessed data comprises the step of performing and operation on the accessed data using an operand.

25. The method of claim 22 wherein said step of writing comprises the substep of reducing a number of the bits output from the arithmetic logic unit and writing a reduced number of bits to the selected array.

26. A memory system comprising:

first and second ports for exchanging data with an external device;

a first data bus for selective coupling to said first port;

a second data bus for selective coupling to said second port;

at least one bank comprising;

an array of dynamic random access memory cells;

a first static random access memory array for selectively exchanging data between said first data bus and said dynamic memory array; and

a second static random access memory array for selectively exchanging data between said second bus and said dynamic memory array; and

circuitry for selectively accessing said dynamic and static arrays in response to a received address bit, said circuitry for accessing comparing said received address bit with a stored address bit and accesses a one of said arrays in response wherein said at least one bank comprises a plurality of banks and said memory further comprises a global row decoder for selecting a one of said plurality of banks for access.

27. The memory of claim 26 wherein said circuitry for accessing selects at least one of said static random access memory arrays when said received address bit and said stored address bit match.

28. The memory of claim 26 wherein each said data port is associated with a dedicated read/write signal for controlling simultaneous reads and writes to said first and second static memory arrays via said first and second buses.

29. The memory of claim 26 wherein said memory comprises a single address port.

30. The memory of claim 26 wherein a simultaneous access to said first and second static memory arrays are performed during a single /RAS cycle.