Memory apparatus and data processor using the same

• US 5,954,435 A
• Filed: 12/13/1996
• Issued: 09/21/1999
• Est. Priority Date: 08/07/1991
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yoshida, Toyohiko
• Primary Examiner(s): Tu, Trinh L.
• Application Number:
  US08/768,021
• Time in Patent Office: 1,012 Days
• Field of Search: 371/21.1, 371/21.2, 371/21.6, 371/51.1, 371/67.1, 371/68.1, 371/71, 371/10.2, 371/10.3, 395/183.18, 395/182.05, 395/182.04, 395/182.03, 395/185.07, 364/245.3, 364/246.3, 364/268.3, 364/268.5, 364/943.91, 364/944, 364/944.2, 364/970.1, 365/189.07, 365/200, 365/201
• US Class Current: 714/42
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

A memory apparatus and a data processor using the same comprises, a memory mechanism, having a signal input terminal into which a predetermined signal is inputted, a memory unit consisting of first, second and third memories, a fourth memory and a control unit which replaces the first or second memory with the third memory by switching electrical connections between the memories of the memory unit according to information written into the fourth memory, and furthermore, an operation unit which diagnoses failures in the memory mechanism in case the predetermined signal is inputted from the signal input terminal, in case the failure is diagnosed in the first memory allows the control unit to replace the first memory with the third memory by writing a first value into the fourth memory, and in case the failure is diagnosed in the second memory allows the control unit to replace the second memory with the third memory by writing a second value into the fourth memory. Since the failure in the memory array unit can be relieved, manufacturing yields of the memory apparatus and the data processor including the same are improved.

Claims

1. In a data processing system including a memory unit having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a spare row of memory cells, a spare column of memory cells, a row decoder for accessing said plurality of memory cells by row, and a plurality of access control bits coupled to said row decoder, each for controlling access to a corresponding one of said plurality of rows, a method for automatically testing and repairing said memory unit comprising the steps of:

(a) testing said memory unit to determine whether said memory unit includes at least one defective memory cell;

(b) repairing said memory unit when said memory unit includes said at least one defective memory cell, wherein said step of repairing produces a modified memory unit and includes the steps of;

(1) calculating a number of defective cells for each of said plurality of columns in said memory unit containing said at least one defective memory cell;

(2) comparing the number of defective cells in one column with the number of defective cells in the other columns;

(3) selecting the column in which the number of defective cells is more than that in another column as a column for replacement; and

(4) substituting said spare column for said selected column for replacement.

2. The method of claim 1, further comprising the steps of:

(c) testing, in an order, each of said plurality of rows of said modified memory unit to determine whether said modified memory unit includes said at least one defective memory cell;

(d) repairing said modified memory unit when said modified memory unit includes said at least one defective memory cell, said step of repairing said modified memory unit including the steps of;

(1) deasserting a corresponding one of said plurality of access control bits for each one of said plurality of rows that contains said at least one defective memory cell;

(2) calculating a number of defective cells of each of said plurality of rows of said modified memory unit containing a defective memory cell;

(3) selecting a row for replacement in said modified memory unit according to a criteria;

(4) substituting said spare row for said row for replacement.

3. The method of claim 2, wherein said row for replacement is a last row in said order that contains said at least one defective memory cell.

4. The method of claim 1, wherein said step of testing said memory unit comprises:

i) writing a predetermined value in each memory cell of said memory unit;

ii) reading one of said plurality of rows of said memory unit to produce an output; and

iii) comparing each bit of said output to said predetermined value to determine whether said one of said plurality of rows includes said at least one defective memory cell;

iv) repeating steps ii) and iii) for each of said plurality of rows until all of said plurality of rows of said memory unit have been tested.

5. The method of claim 4, wherein said step of calculating said number of defective cells comprises the steps of:

1) recording, for each of said plurality of rows of said memory unit, a column number corresponding to said at least one defective memory cell in said one of said plurality of rows of said memory unit; and

2) counting each incidence of said column number being so recorded.

6. The method of claim 1, wherein said step of substituting said spare column for said column for replacement includes the steps of:

de-coupling a data line coupled to said column for replacement; and

coupling said data line to said spare column.

7. In a data processing system including a memory unit having a plurality of memory cells arranged in a plurality of rows and a plurality of columns, a spare row of memory cells, a spare column of memory cells, a row decoder for accessing said plurality of memory cells by row, and a plurality of access control bits coupled to said row decoder, each for controlling access to a corresponding one of said plurality of rows, a method for automatically testing and repairing said memory unit comprising the steps of:

(a) testing said memory unit to determine whether said memory unit includes at least one defective memory cell;

(b) repairing said memory unit when said memory unit includes said at least one defective memory cell, wherein said step of repairing produces a modified memory unit and includes the steps of;

(1) calculating a number of defective cells for each of said plurality of columns in said memory unit containing said at least one defective memory cell;

(2) selecting a column for replacement in said memory unit according to said number of defective cells, wherein said column for replacement is a column in said memory unit having a greatest number of defective cells; and

(3) substituting said spare column for said selected column for replacement.

8. The method of claim 7, further comprising the steps of:

(c) testing, in an order, each of said plurality of rows of said modified memory unit to determine whether said modified memory unit includes at least one defective memory cell;

(d) repairing said modified memory unit when said modified memory unit includes said at least one defective memory cell, said step of repairing said modified memory unit including the steps of;

(1) deasserting a corresponding one of said plurality of access control bits for each one of said plurality of rows that contains said at least one defective memory cell;

(2) calculating a number of defective cells for each of said plurality of rows of said modified memory unit containing a defective memory cell;

(3) selecting a row for replacement in said modified memory unit according to a criteria;

(4) substituting said spare row for said row for replacement.

9. The method of claim 8, wherein said row for replacement is a last row in said order that contains said at least one memory cell.

10. The method of claim 7, wherein said step of testing said memory unit comprises:

i) writing a predetermined value in each memory cell of said memory unit;

ii) reading one of said plurality of rows of said memory unit to produce an output; and

iii) comparing each bit of said output to said predetermined value to determine whether said one of said plurality of rows includes said at least one defective memory cell;

iv) repeating steps ii) and iii) for each of said plurality of rows until all of said plurality of rows of said memory unit have been tested.

11. The method of claim 10, wherein said step of calculating said number of defective cells comprises the steps of:

1) recording, for each of said plurality of rows of said memory unit, a column number corresponding to said at least one defective memory cell in said one of said plurality of rows of said memory unit; and

2) counting each incidence of said column number being so recorded.

12. The method of claim 7, wherein said step of substituting said spare column for said selected column for replacement includes the steps of:

de-coupling a data line coupled to said selected column for replacement; and

coupling said data line to said spare column.