Synchronous memory device having an internal register

• US 5,954,804 A
• Filed: 02/10/1997
• Issued: 09/21/1999
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US08/798,525
• Time in Patent Office: 953 Days
• Field of Search: 395/423, 395/441, 395/871, 395/829, 398/871, 398/829, 398/423, 398/441, 398/224, 377/2, 710/3-4, 710/8-10, 710/36-51, 710/58-61, 710/104-125, 710/129-130, 711/167-173
• US Class Current: 710/36
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention is directed to an integrated circuit device having at least one memory section including a plurality of memory cells. The device includes an internal register to store an identification value which identifies the device on a bus. The device further includes interface circuitry, coupled to the bus, to receive identification information and a read request. The interface circuitry includes a plurality of output drivers and comparison circuitry. The output drivers are coupled to the bus to output data on the bus in response to the read request. The data is output synchronously with respect to first and second external clock signals when the comparison circuitry determines the identification information corresponds to the identification value.

Claims

1. A synchronous memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises:

a first internal register to store an identification value to identify the memory device on an external bus;

interface circuitry, coupled to the bus, to receive a transaction request packet including identification information,

comparison circuitry, coupled to the interface circuitry and the first internal register, to determine whether the identification information corresponds to the identification value in the first internal register wherein when the identification information corresponds to the identification value, the memory device responds to the transaction request packet.

2. The memory device of claim 1 wherein the first internal register stores a unique identification value to identify the memory device from a plurality of other memory devices on the bus.

3. The memory device of claim 1 wherein the first internal register stores a special device identification value to identify the memory device and a plurality of other memory devices on the bus.

4. The memory device of claim 1 wherein the interface circuitry further includes:

clock receiver circuitry to receive a first external clock signal; and

an output driver to output data synchronously with respect to the first external clock signal.

5. The memory device of claim 4 further including a delay locked loop to generate a first internal clock signal using at least the first external clock signal wherein, in response to the first internal clock signal, the output driver outputs data on the bus.

6. The memory device of claim 1 wherein the interface circuitry further includes:

clock receiver circuitry to receive a first external clock signal and a second external signal; and

an output driver to output data on the bus synchronously with respect to the first and second external clock signals.

7. The memory device of claim 6 further including a delay locked loop which is coupled to the clock receiver circuitry to receive the first and second external clock signals and generate a first internal clock signal using the first and second external clock signals, wherein the output driver, in response to the first internal clock signal, outputs data on the bus.

8. The memory device of claim 7 wherein the first and the second external clock signals are complementary.

9. The memory device of claim 6 further including a first delay locked loop to generate a first internal clock signal and a second delay locked loop to generate a second internal clock signal wherein, in response to the first and second internal clock signals, the output driver outputs data on the bus.

10. The memory device of claim 9 wherein the first delay locked loop generates the first internal clock signal using the first and the second external clock signals.

11. The memory device of claim 10 further including a multiplexer coupled to the delay locked loop to receive the first and the second internal clock signals, the multiplexer includes a first input coupled to a first internal data bus line and a second input coupled to a second internal data bus line, wherein the multiplexer couples the first internal data bus line to an input of the output driver in response to the first internal clock signal and couples the second internal data bus line to the input of the output driver in response to the second internal clock signal.

12. The memory device of claim 11 further including a second internal register to store a value which is representative of a number of clock cycles to transpire before the memory device responds to a read request wherein the output driver outputs data on the bus in accordance with the value stored in the second internal register.

13. The memory device of claim 10 wherein the output driver outputs data in response to a rising edge of the first internal clock signal and in response to a rising edge of the second internal clock signal.

14. The memory device of claim 1 wherein the interface circuitry further includes:

clock receiver circuitry to receive a first external clock signal; and

input receiver circuitry to latch information on the bus synchronously with respect to the first external clock signal when the identification information corresponds to the identification value.

15. An integrated circuit device having at least one memory section which includes a plurality of memory cells, wherein the integrated circuit device outputs data on an external bus synchronously with respect to first and second external clock signals, the integrated circuit device comprises:

a programmable internal register to store an identification value to identify the integrated circuit device on the external bus; and

interface circuitry, coupled to the external bus, to receive identification information and a read request from the external bus, the interface circuitry includes;

a plurality of output drivers, each output driver being coupled to the external bus; and

comparison circuitry, coupled to the interface circuitry to receive the identification information, the comparison circuitry determines whether the identification information corresponds to the identification value in the internal register wherein when the identification information corresponds to the identification value, the integrated circuit device responds to the read request and the plurality of output drivers output data on the external bus in response to the read request and synchronously with respect to the first and second external clock signals.

16. The integrated circuit device of claim 15 wherein the internal register stores a unique identification value to identify the integrated circuit device from a plurality of other devices on the bus.

17. The integrated circuit device of claim 15 wherein the internal register stores a special identification value to identify the integrated circuit device and a plurality of other devices on the bus.

18. The integrated circuit device of claim 15 wherein the interface circuitry further includes input receiver circuitry to latch the read request on the bus synchronously with respect to the first external clock signal when the identification information corresponds to the identification value.

19. The integrated circuit device of claim 15 further including a delay locked loop to generate a first internal clock signal using at least the first external clock signal wherein a plurality of the output drivers output data on the bus in response to the first internal clock signal.

20. The integrated circuit device of claim 15 wherein the first and the second external clock signals are complementary.

21. The integrated circuit device of claim 15 wherein the delay locked loop generates a first internal clock signal and a second internal clock signal and wherein the plurality of output drivers output data on the bus in response to a rising edge of the first internal clock signal and in response to a rising edge of the second internal clock signal.

22. The integrated circuit device of claim 15 further including a first delay locked loop to generate a first internal clock signal and a second delay locked loop to generate a second internal clock signal wherein the plurality of output drivers output data on the bus in response to the first internal clock signal and in response to the second internal clock signal.

23. An integrated circuit device having at least one memory section which includes a plurality of memory cells, wherein the integrated circuit device outputs data on an external bus synchronously with respect to first and second external clock signals, the integrated circuit device comprises:

a first internal register to store a value which is representative of a number of clock cycles to transpire before the integrated circuit device responds to a read request;

a second internal register to store an identification value to identify the integrated circuit device on the external bus;

delay locked loop circuitry to generate a first internal clock signal using the first and second external clock signals; and

interface circuitry, coupled to the external bus to receive identification information and a read request, the interface circuitry includes;

at least one output driver, coupled to the external bus, to output data on the external bus in response to the first internal clock signal and synchronously with respect to the first and second external clock signals; and

comparison circuitry, coupled to the interface circuitry, to determine whether the identification information corresponds to the identification value in the internal register wherein when the identification information corresponds to the identification value, the integrated circuit device responds to the read request.

24. The integrated circuit device of claim 23 wherein the output driver outputs data on the external bus in accordance with the value stored in the first internal register.

25. The integrated circuit device of claim 23 wherein the delay locked loop circuitry generates the first internal clock signal using the first and second external clock signals and generates a second internal clock signal and wherein the output driver outputs data on the bus in response to the first and the second internal clock signals.

26. An integrated circuit device having at least one memory section which includes a plurality of memory cells, wherein the integrated circuit device outputs data on an external bus synchronously with respect to first and second external clock signals, the integrated circuit device comprises:

a first internal register to store a value which is representative of a number of clock cycles to transpire before the integrated circuit device responds to a read request;

delay locked loop circuitry to generate an internal clock signal using the first and second external clock signals; and

interface circuitry, coupled to the external bus to receive a read request, the interface circuitry includes a plurality of output drivers, coupled to the external bus, to output data on the external bus in response to the internal clock signal, synchronously with respect to the first and second external clock signals and in accordance with the value stored in the first internal register.