Digital signal processor architecture

• US 5,954,811 A
• Filed: 01/25/1996
• Issued: 09/21/1999
• Est. Priority Date: 01/25/1996
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Garde, Douglas
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/591,137
• Time in Patent Office: 1,335 Days
• Field of Search: 395/477, 395/480, 395/405, 395/800.35, 395/800.23, 395/381, 711/150, 711/153, 711/123, 711/119, 711/168, 711/214, 711/5, 365/189.04, 365/220, 365/230.03
• US Class Current: 712/35
• CPC Class Codes: G06F 15/7857 using interleaved memory addressing G06F12/0607
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A high performance digital signal processor includes a memory for storing instructions and operands for digital signal computations and a core processor connected to the memory. The memory includes first, second and third memory banks connected to the core processor by first, second and third data and address buses, respectively. The core processor includes a program sequencer and first and second computation blocks for performing first and second subsets, respectively, of the digital signal computations. Single, dual or quad data words of 32 bits each may be accessed in each of the memory banks during each clock cycle. The multiple data words may be transferred to one or both of the first and second computation blocks.

Claims

1. A digital signal processor comprising:

a memory including a first memory bank for storing instructions and second and third memory banks for storing operands for digital signal computations;

a core processor connected to said first, second and third memory banks, said core processor comprising;

a program sequencer for generating instruction addresses for fetching selected ones of said instructions from said first memory bank; and

a computation unit for performing said digital signal computations using said instructions and said operands, said computation unit including a first computation block for performing a first subset of said digital signal computations using a first subset of said instructions and a first subset of said operands, and a second computation block for performing a second subset of said digital signal computations using a second subset of said instructions and a second subset of said operands; and

transfer selection means responsive to said instructions for simultaneously addressing quad operands in a single row of one or both of said second and third memory banks and selectably and simultaneously providing one, two or four of said quad operands to said computation unit for performing said digital signal computations, wherein each of said second and third memory banks is organized as quad word rows and wherein said transfer selection means includes means for selectably accessing single, dual or quad locations in a selected quad word row and each of said first and second computation blocks includes means for selecting the operands accessed in one or both of said second and third memory banks.

2. A digital signal processor as defined in claim 1 wherein said operands each comprise 32 bits, such that said second and third memory banks each provide up to 128 bits during each clock cycle.

3. A digital signal processor as defined in claim 1 wherein said transfer selection means further includes means for selectably writing single, dual or quad data words in one or both of said second and third memory banks during each clock cycle.

4. A digital signal processor as defined in claim 1 wherein said program sequencer includes means for fetching an instruction line including plural instructions from said first memory bank during each clock cycle.

5. A digital signal processor as defined in claim 1 wherein said first and second subsets of said instructions are the same.

6. A digital signal processor as defined in claim 1 wherein said first and second subsets of said instructions are different.

7. A digital signal processor as defined in claim 1 further including first data and address buses interconnecting said core processor and said first memory bank, second data and address buses interconnecting said core processor and said second memory bank, and third data and address buses interconnecting said core processor and said third memory bank.

8. A digital signal processor as defined in claim 7 wherein each of said first, second and third data buses is 128 bits wide for transferring up to four data words of 32 bits each during each clock cycle.

9. A digital signal processor as defined in claim 1 wherein said first and second computation blocks each include a register file for temporary storage of operands and results, a multiplier for performing multiplication operations, an ALU for performing arithmetic operations and a shifter for performing shifting operations.

10. A digital signal processor as defined in claim 1 wherein said second and third memory banks are organized as quad word rows and wherein said transfer selection means includes means for enabling said first and second computation blocks to write to different words of a selected quad word row during each clock cycle.

11. A digital signal processor as defined in claim 1 wherein said transfer selection means includes means for selectably transferring dual operands in a quad operand to one or both of said first and second computation blocks during each clock cycle.

12. A digital signal processor as defined in claim 1 wherein said transfer selection means includes means for selectably transferring single operands in a dual operand to one or both of said first and second computation blocks during each clock cycle.

13. A digital signal processor as defined in claim 1 wherein said transfer selection means includes means for selectably transferring a quad operand to one or both of said first and second computation blocks during each clock cycle.

14. A digital signal processor as defined in claim 1 wherein said transfer selection means includes means for selectably accessing up to eight operands of 32 bits each during each clock cycle.

15. A digital signal processor as defined in claim 1 wherein said first memory bank is organized as quad word rows and wherein said instructions are stored in first memory bank as instruction lines of up to four instructions, wherein the instructions of an instruction line are stored in one or two quad word rows of said first memory bank.

16. A digital signal processor as defined in claim 15 wherein said core processor further includes an instruction alignment buffer for aligning instructions that are read from said first memory bank on different clock cycles but are required to be executed in one clock cycle.

17. A digital signal processor as defined in claim 1 wherein said transfer selection means includes means for writing results of said digital signal computations from said computation unit to one or both of said second and third memory banks during each clock cycle.

18. A digital signal processor as defined in claim 1 further including a first data address generator for generating addresses for fetching selected ones of said operands from said second memory bank and a second data address generator for generating addresses for fetching selected ones of said operands from said third memory bank.

19. A digital signal processor comprising:

a memory including a first memory bank for storing instructions and second and third memory banks for storing operands for digital signal computations;

a core processor comprising;

a program sequencer for generating instruction addresses for fetching selected ones of said instructions from said first memory bank; and

a computation unit for performing said digital signal computations using said instructions and said operands, said computation unit including a first computation block for performing a first subset of said digital signal computations using a first subset of said instructions and a first subset of said operands, and a second computation block for performing a second subset of said digital signal computations using a second subset of said instructions and a second subset of said operands;

first data and address buses interconnecting said core processor and said first memory bank, second data and address buses interconnecting said core processor and said second memory bank, and third data and address buses interconnecting said core processor and said third memory bank, said first, second and third data buses each being 128 bits wide; and

transfer selection means responsive to said instructions for simultaneously addressing quad operands of 32 bits each in a single row of one or more of said second and third memory banks and selectably and simultaneously providing one, two or four of said quad operands to said computation unit for performing said digital signal computations, wherein each of said second and third memory banks is organized as quad word rows and wherein said transfer selection means includes means for selectably accessing single, dual or quad locations in a selected quad word row and each of said first and second computation blocks includes means for selecting the operands accessed in one or both of said second and third memory banks.

20. A method for digital signal processing comprising the steps of:

storing instructions for digital signal computations in a first memory bank and storing operands for the digital signal computations in a second memory bank;

generating instruction addresses for fetching selected ones of said instructions from said first memory bank;

simultaneously addressing quad operands in a single row of said second memory bank and selectably and simultaneously providing one, two or four of said quad operands to a computation unit for performing said digital signal computations, said computation unit including a first computation block for performing a first subset of said digital signal computations using a first subset of said instructions and a first subset of said operands, and a second computation block for performing a second subset of said digital signal computations using a second subset of said instructions and a second subset of said operands, wherein said second memory bank is organized as quad word rows and wherein the steps of simultaneously addressing quad operands and selectably and simultaneously providing one, two or four of said quad operands include accessing single, dual or quad locations in a selected quad row and each of said first and second computation blocks selects the operands accessed in said second memory bank; and

said computation unit performing said digital signal computations using said instructions from said first memory bank and said operands from said second memory bank.

21. A method as defined in claim 20 further including the step of storing operands for the digital signal computations in a third memory bank and wherein the steps of simultaneously addressing quad operands and selectably and simultaneously providing one, two or four of said quad operands include selectably accessing said single, dual or quad operands in one or both of said second and third memory banks during each clock cycle.

22. A method as defined in claim 20 further including the steps of storing instructions being executed in an instruction cache, fetching instructions for execution from said instruction cache and storing operands in said first memory bank, and wherein the step of selectably accessing single, dual or quad operands includes selectably accessing single, dual or quad operands in one or both of said first and second memory banks.

23. A digital signal processor comprising:

a memory including a first memory bank for storing instructions and a second memory bank for storing operands for digital signal computations;

a core processor connected to said first and second memory banks, said core processor comprising;

a program sequencer for generating instruction addresses for fetching selected ones of said instructions from said first memory bank; and

a computation unit for performing said digital signal computations using said instructions and said operands, said computation unit including a first computation block for performing a first subset of said digital signal computations using a first subset of said instructions and a first subset of said operands, and a second computation block for performing a second subset of said digital signal computations using a second subset of said instructions and a second subset of said operands; and

transfer selection means responsive to said instructions for simultaneously addressing quad operands in a single row of said second memory bank and selectably and simultaneously providing one, two or four of said quad operands to said computation unit for performing said digital signal computations, wherein said second memory bank is organized as quad word rows and wherein said transfer selection means includes means for selectably accessing single, dual or quad locations in a selected quad word row and each of said first and second computation blocks includes means for selecting the operands accessed in said second memory bank.

24. A digital signal processor comprising:

a memory including a first memory bank for storing instructions and operands and a second memory bank for storing operands for digital signal computations;

a core processor connected to said first and second memory banks, said core processor comprising;

an instruction cache for storing a subset of said instructions;

a program sequencer for generating instruction addresses for fetching selected ones of said instructions from said instruction cache or said first memory bank; and

a computation unit for performing said digital computations using said instructions and said operands, said computation unit including a first computation block for performing a first subset of said digital signal computations using a first subset of said instructions and a first subset of said operands, and a second computation block for performing a second subset of said digital signal computations using a second subset of said instructions and a second subset of said operands; and

transfer selection means responsive to said instructions for simultaneously addressing quad operands in a single row of one or both of said first and second memory banks and selectably and simultaneously providing one, two or four of said quad operands to said computation unit for performing said digital signal computations, wherein each of said first and second memory banks is organized as quad word rows and wherein said transfer selection means includes means for selectably accessing single, dual or quad locations in a selected quad word row and each of said first and second computation blocks includes means for selecting the operands accessed in one or both of said first and second memory banks.