Test mode matrix circuit for an embedded microprocessor core

• US 5,954,824 A
• Filed: 09/11/1997
• Issued: 09/21/1999
• Est. Priority Date: 08/07/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Colyer, Peter Stewart, Stauffer, David Robert, Cherichetti, Cory Ansel
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US08/927,236
• Time in Patent Office: 740 Days
• Field of Search: 395/183.04, 395/183.01, 395/183.06, 371/25.1, 371/22.5, 371/22.6, 364/267.91, 364/550, 364/578, 364/927.81, 714/28, 714/25, 714/30, 714/736, 714/733, 714/734, 307/407, 307/412
• US Class Current: 714/28
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A test mode matrix circuit in an integrated circuit switches signal lines internal to the integrated circuit in a manner that allows an embedded microprocessor within the integrated circuit to be fully functionally tested using standard test vectors applied to the integrated circuit, and which allows for debugging the code written for an embedded microprocessor core by connecting an in-circuit emulator (ICE) to the integrated circuit. The test mode matrix circuit operates in a number of mutually exclusive modes, each of which is suitably selected via control signal inputs to the test mode matrix. The test mode matrix circuit couples signals from the embedded microprocessor to the application-specific logic without passing through off-chip drivers/receivers. Multiple microprocessors and corresponding test mode matrices may also be implemented on the same integrated circuit.

Claims

1. An integrated circuit comprising:

at least one microprocessor;

a plurality of I/O circuits coupled to a plurality of I/O pads, wherein the plurality of I/O circuits comprise a plurality of I/O drivers and I/O receivers;

a logic circuit; and

a switch means coupled between the microprocessor and the logic circuit, wherein the switch means operates in one of a plurality of mutually-exclusive states, and wherein the switch means routes the microprocessor operational signals to the logic circuit without passing through any I/O drivers that are coupled to I/O pads on the integrated circuit and without passing through any I/O receivers that are coupled to the I/O pads in a first of the plurality of states, routes the microprocessor test signals from the plurality of I/O circuits to the microprocessor in a second of the plurality of states, and routes the logic test signals from the plurality of I/O circuits to the logic circuit in a third of the plurality of states.

2. The integrated circuit of claim 1 wherein the switch means contains no three-state devices.

3. The integrated circuit of claim 1 further comprising means for selecting one of the plurality of states.

4. The integrated circuit of claim 1 wherein the first state of the switch means corresponds to a state for normally operating the integrated circuit, wherein the second state of the switch means corresponds to a state for testing the microprocessor by applying standard test vectors for the microprocessor to the plurality of I/O pads, and wherein the third state of the switch means corresponds to a state for testing the integrated circuit by coupling an in-circuit emulator to the plurality of I/O pads.

5. The integrated circuit of claim 1 wherein the switch means comprises at least one test mode matrix, each test mode matrix comprising a plurality of cells, each cell coupled to at least one of the plurality of I/O circuits, each cell further comprising:

means for coupling at least one signal between the microprocessor and the logic circuit in the first state;

means for coupling at least one signal between at least one of the plurality of I/O circuits and the microprocessor in the second state; and

means for coupling at least one signal between at least one of the plurality of I/O circuits and the logic circuit in the third state.

6. The integrated circuit of claim 1 wherein the switch means routes auxiliary test signals from the integrated circuit to the plurality of I/O circuits when the signal routing means is in a fourth state.

7. The integrated circuit of claim 1 comprising a plurality of microprocessors, and further comprising a means for selecting one of the plurality of microprocessors.

8. The integrated circuit of claim 1 comprising a plurality of microprocessors, and wherein the switch means comprises:

a plurality of test mode matrices, at least one test mode matrix for each of the microprocessors; and

a means for coupling the test mode matrices corresponding to a selected one of the plurality of microprocessors to the plurality of I/O circuits.

9. A method for testing an integrated circuit comprising the steps of:

providing a microprocessor on the integrated circuit;

providing a logic circuit on the integrated circuit;

providing a plurality of I/O circuits on the integrated circuit that are coupled to a plurality of I/O pads on the integrated circuit, wherein the plurality of I/O circuits comprise a plurality of I/O drivers and I/O receivers;

providing switch means coupled between the microprocessor and the logic circuit, wherein the switch means operates in one of a plurality of mutually-exclusive states, and wherein the switch means routes microprocessor operational signals directly to the logic circuit without passing through any I/O circuits in a first of the plurality of states, routes microprocessor test signals to the microprocessor in a second of the plurality of states, and routes logic test signals to the logic circuit in a third of the plurality of states;

routing the microprocessor test signals from an external tester that is coupled to at least one I/O pad; and

applying test vectors to the microprocessor through the switch means.

10. The method of claim 9 further comprising the step of the switch means routing the logic test signals from an external in-circuit emulator which emulates the function of the microprocessor for debugging the logic circuit and for debugging code for the microprocessor.