Non-volatile memory device for fault tolerant data
First Claim
1. A non-volatile memory device, comprising:
- an integrated circuit;
an array of floating gate memory cells on the integrated circuit;
read, erase, program and verify control logic for the array on the integrated circuit; and
a status register on the integrated circuit, coupled with the control logic, to store defect statistics for a program operation in which a plurality of bytes is programmed to the array, and the defect statistics characterize defects determined during verify operations concerning the plurality of bytes, and logic coupled with the status register which overwrites the defect statistics of a previous program operation.
1 Assignment
0 Petitions
Accused Products
Abstract
A non-volatile memory device based on an array of floating gate memory cells includes read, erase, program and verify control logic for the array. A status register is coupled with the control logic and stores statistics determined during verify operations concerning at least one of the erase and program operations. For instance, the control logic may include erase verify resources and program verify resources, and the statistics will indicate a number of memory cells which fail erase or program verify. Alternatively, the statistics may indicate whether a threshold number of sequential bytes in the memory fail program verify for a program or erase operation involving a page or sector of data. In addition, defective addresses can be stored. With the status register, the number of program and erase retries for the device can be significantly reduced, allowing application of the device to real time storage systems. Many real time storage problems are fault tolerant. That is, a number of errors in a large amount of data will not be significant. Thus, the user of the device can rely on the status register to indicate how many errors have been detected in the array. If more than a threshold number of errors is detected, then the data can be discarded. However, for fault tolerant applications, the device will store a significant amount of data with few errors which will not affect operation of the system.
-
Citations
76 Claims
-
1. A non-volatile memory device, comprising:
-
an integrated circuit; an array of floating gate memory cells on the integrated circuit; read, erase, program and verify control logic for the array on the integrated circuit; and a status register on the integrated circuit, coupled with the control logic, to store defect statistics for a program operation in which a plurality of bytes is programmed to the array, and the defect statistics characterize defects determined during verify operations concerning the plurality of bytes, and logic coupled with the status register which overwrites the defect statistics of a previous program operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A non-volatile memory device, comprising:
-
an integrated circuit; an array of floating gate memory cells on the integrated circuit, and the array including a first section and a second section; and read, erase, program and verify control logic for the array on the integrated circuit, and the control logic including circuitry which retries a program operation in which a plurality of bytes is programmed to the array for bits in the plurality of bytes programmed to the first section of the array which fail program verify until a first maximum retry count is reached, and which retries program operations for bits in a plurality of bytes programmed to the second section of the array which fail program verify until a second maximum retry count is reached, and the first maximum retry count being greater than the second maximum retry count. - View Dependent Claims (17, 18)
-
-
19. A non-volatile memory device for fault tolerant data storage, comprising:
-
an array of floating gate memory cells; a data input, which receives an input data stream; a buffer memory, coupled to the input, which receives data from the data input and applies the received data to the array for programming; erase, program and verify control logic, coupled to the buffer memory, including resources for programming the array with data from the buffer memory, and for erasing at least portions of the array; a volatile status register, coupled with the control logic, to store defect statistics characterizing defects determined during verify operations concerning at least one of programming and erasing operations; and read control logic, coupled to the array and to the status register, providing read access to the array and to the status register. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
-
-
32. A non-volatile memory device for fault tolerant data storage, comprising:
-
an array of floating gate memory cells and the array including a first section and a second section; a data input, which receives an input data stream; a buffer memory, coupled to the input, which receives data from the data input and applies the received data to the array for programming; erase, program and verify control logic, coupled to the buffer memory, including resources for programming the array with data from the buffer memory, and for erasing at least portions of the array, and the control logic including circuitry which retries program operations for bits in a particular byte programmed to the first section of the array which fail program verify until a first maximum retry count is reached and if the first maximum retry count is reached for the particular byte, then signals program failure, and which retries program operations for bits in a particular byte programmed to the second section of the array which fail program verify until a second maximum retry count is reached and if the second maximum retry count is reached for the particular byte, then logs a defect, and the first maximum retry count being greater than the second maximum retry count; and read control logic, coupled to the array and to the status register, providing read access to the array. - View Dependent Claims (33)
-
-
34. A non-volatile memory device for real-time, fault tolerant data storage, comprising:
-
an array of non-volatile, floating gate memory cells; a data input which receives input data; a page program buffer, coupled to the data input, which receives the input data and applies a page of input data in parallel to the array for programming, the page including more than 32 bits; erase, program and verify control logic, coupled to the page program buffer, including resources for programming the array with data from the page program buffer, and including resources for erasing selected segments of data in the array; a status register comprising volatile storage cells, coupled with the erase, program and verify control logic, to store defect statistics characterizing defects determined during verify operations; and read control logic, coupled to the array and to the status register, providing read access to the array and to the status register. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
-
-
47. A non-volatile memory device for real-time, fault tolerant data storage, comprising:
-
an array of non-volatile, floating gate memory cells, and the array including a first section and a second section; a data input which receives input data; a page program buffer, coupled to the data input, which receives the input data and applies a page of input data in parallel to the array for programming, the page including more than 32 bits; erase, program and verify control logic, coupled to the page program buffer, including resources for programming the array with data from the page program buffer, and including resources for erasing selected segments of data in the array; and read control logic coupled to the array, and the control logic providing read access to the array, and the control logic including circuitry which retries page programming operations for bits in a particular byte programmed to the first section of the array which fail program verify until a first maximum retry count is reached and if the first maximum retry count is reached for the particular byte programmed to the first section of the array, then signals program failure, and which retries page programming operations for bits in a particular byte programmed to the second section of the array which fail program verify until a second maximum retry count is reached and if the second maximum retry count is reached for the particular byte programmed to the second section of the array, then logs a program defect; and
the first maximum retry count being greater than the second maximum retry count. - View Dependent Claims (48, 49)
-
-
50. A method for storing data on an integrated circuit having an array of floating gate memory cells, comprising:
-
programming a segment of data to the array, the segment including a plurality of bytes of data; executing a verify operation for the segment; determining during the verify operation defect statistics characterizing defects in the programmed segment; storing the defect statistics on the integrated circuit; reading the defect statistics from the integrated circuit after the program operation; and clearing the defect statistics from the integrated circuit. - View Dependent Claims (51, 52, 53, 54, 55)
-
-
56. A non-volatile memory device, comprising:
-
an array of floating gate memory cells; read, erase, program and verify control logic for the array, including program verify resources; and a status register, coupled with the control logic, to store defect statistics which characterize defects determined during verify operations concerning a program operation in which a plurality of bytes were programmed to the array, including defect statistics indicating whether a threshold number of sequential bytes fail program verify, and logic coupled with the status register which overwrites the defect statistics of a previous program operation. - View Dependent Claims (57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 76)
-
-
67. A non-volatile memory device, comprising:
-
an array of floating gate memory cells, and the array including a first section and a second section; and read, erase, program and verify control logic for the array, including program verify resources, and the control logic including circuitry which retries program operations for bits in a byte programmed to the first section of the array which fail program verify until a first maximum retry count is reached, and which retries program operations for bits in a byte programmed to the second section of the array which fail program verify until a second maximum retry count is reached, and the first maximum retry count being greater than the second maximum retry count. - View Dependent Claims (68, 69)
-
-
70. A method for storing data on an integrated circuit having an array of floating gate memory cells, comprising:
-
programming a segment of data to the array, the segment including a plurality of bytes of data; executing a verify operation for the segment; determining during the verify operation defect statistics characterizing defects in the programmed segment; storing the defect statistics on the integrated circuit; reading the defect statistics from the integrated circuit after the program operation; and overwriting the defect statistics on the integrated circuit. - View Dependent Claims (71, 72, 73, 74, 75)
-
Specification