Selector and decision wait using pass gate XOR

• US 5,955,898 A
• Filed: 06/30/1997
• Issued: 09/21/1999
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Lexau, Jon K., Sutherland, Ivan E., Coates, William S.
• Primary Examiner(s): Ellis, Richard L.
• Application Number:
  US08/885,169
• Time in Patent Office: 813 Days
• Field of Search: 395/309, 395/310, 395/311, 395/312, 395/728, 395/729, 395/730, 395/731, 395/732, 395/551, 395/552, 395/555, 395/556, 395/557, 395/558, 395/899, 326/52, 326/53, 326/54, 326/55, 326/17, 326/37, 326/96, 326/99, 326/21, 326/39, 326/41, 326/121, 326/40, 326/113, 326/93, 326/38, 327/403, 327/404, 327/141
• US Class Current: 326/121
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A logic gate includes a plurality of pass gates forming a double rail pass gate XOR or reversing switch providing the same functionality as a conventional XOR gate. Consequently, the pass gate XOR can substitute for XOR gates in circuits such as a selector circuit and decision wait circuit, but with faster responses and fewer transistors than the conventional XOR gate. Each pass gate includes a P-type and an N-type transistor coupled in parallel. A control input and its complement are coupled to the gates of the transistors to selectively pass signals at the input of the pass gate to its output.

Claims

1. A selector circuit for a logic gate receiving

first and second complementary control signals,

first and second complementary input signals,

first and second complementary primary output signals,

first and second complementary secondary output signals, and

first and second waiton gates each having complementary inputs and outputs, the outputs of the first waiton gate producing the primary output signals, and the outputs of the second waiton gate producing the secondary output signals, the selector circuit comprising:

a first reversing switch including four pass gates,

a first one of the pass gates being coupled to a first one of the inputs of the first waiton gate, being coupled to receive one of the first input signal or the second secondary output signal, and being responsive to the other one of the first input signal or the second secondary output signal,

a second one of the pass gates being coupled to a second one of the inputs of the first waiton gate, being coupled to receive one of the second input signal or the first secondary output signal, and being responsive to the other one of the second input signal or the first secondary output signal,

a third one of the pass gates being coupled to a second one of the inputs of the first waiton gate, being coupled to receive one of the first input signal or the second secondary output signal, and being responsive to the other one of the first input signal or the second secondary output signal, and

a fourth one of the pass gates being coupled to a first one of the inputs of the first waiton gate, being coupled to receive one of the second input signal or the first secondary output signal, and being responsive to the other one of the second input signal or the first secondary output signal; and

a second reversing switch including four pass gates,

a first one of the pass gates being coupled to a first one of the inputs of the second waiton gate and, being coupled to receive one of the first input signal or the second primary output signal, and being responsive to the other one of the first input signal or the second primary output signal,

a second one of the pass gates being coupled to a second one of the inputs of the second waiton gate and, being coupled to receive one of the second input signal or the first primary output signal, and being responsive to the other one of the second input signal or the first primary output signal,

a third one of the pass gates being coupled to a second one of the inputs of the second waiton gate and, being coupled to receive one of the first input signal or the second primary output signal, and being responsive to the other one of the first input signal or the second primary output signal, and

a fourth one of the pass gates being coupled to a first one of the inputs of the first waiton gate and, being coupled to receive one of the second input signal or the first primary output signal, and being responsive to the other one of the second input signal or the first primary output signal.

2. A decision wait circuit for a logic gate receiving

first and second complementary control signals,

first and second complementary primary input signals,

first and second complementary secondary input signals,

first and second complementary primary output signals,

first and second complementary secondary output signals, and

first and second Muller C-elements each having complementary primary and secondary inputs and complementary outputs, the primary inputs of the first Muller C-element receiving the primary input signals, the primary inputs of the second Muller C-element receiving the secondary input signals, the outputs of the first Muller C-element producing the primary output signals, and the outputs of the second Muller C-element producing the secondary output signals, the decision wait circuit comprising:

a first reversing switch including four pass gates,

a first one of the pass gates being coupled to a first one of the secondary inputs of the first Muller C-element, being coupled to receive one of the first control signal or the second secondary output signal, and being responsive to the other one of the first control signal or the second secondary output signal,

a second one of the pass gates being coupled to a second one of the secondary inputs of the first Muller C-element, being coupled to receive one of the second control signal or the first secondary output signal, and being responsive to the other one of the second control signal or the first secondary output signal,

a third one of the pass gates being coupled to a second one of the secondary inputs of the first Muller C-element, being coupled to receive one of the first control signal or the second secondary output signal, and being responsive to the other one of the first control signal or the second secondary output signal, and

a fourth one of the pass gates being coupled to a first one of the secondary inputs of the first Muller C-element, being coupled to receive one of the second control signal or the first secondary output signal, and being responsive to the other one of the second control signal or the first secondary output signal; and

a second reversing switch including four pass gates,

a first one of the pass gates being coupled to a first one of the secondary inputs of the second Muller C-element and, being coupled to receive one of the first control signal or the second primary output signal, and being responsive to the other one of the first control signal or the second primary output signal,

a second one of the pass gates being coupled to a second one of the secondary inputs of the second Muller C-element and, being coupled to receive one of the second control signal or the first primary output signal, and being responsive to the other one of the second control signal or the first primary output signal,

a third one of the pass gates being coupled to a second one of the secondary inputs of the second Muller C-element and, being coupled to receive one of the first control signal or the second primary output signal, and being responsive to the other one of the first control signal or the second primary output signal, and

a fourth one of the pass gates being coupled to a first one of the secondary inputs of the first Muller C-element and, being coupled to receive one of the second control signal or the first primary output signal, and being responsive to the other one of the second control signal or the first primary output signal.