Switch with programmable delay
First Claim
Patent Images
1. An integrated circuit comprising:
- an error amplifier, connected to receive a voltage sense signal and a reference signal, so as to produce an error control signal;
a ramp node for providing a periodic ramp signal;
a reset signal generator arranged so as to produce a reset signal;
a comparator connected to receive the error control signal and the ramp signal for generating a first state signal or a second state signal depending upon a comparison between the error control signal and the ramp signal;
a latch circuit coupled to said reset signal generator and to said comparator in order to latch the first state signal until the reset signal is received; and
an output driver, connected to a first terminal and a second terminal, switched in response to the first and second state signals to drive an output signal on the first terminal in response to the first state signal and to provide a low impedance path between the first terminal and the second terminal in response to the second state signal.
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Abstract
A programmable delay circuit employs a comparator to control an output driver. The comparator compares a ramp signal to an error control signal derived from an error amplifier or in the alternative to a disable signal. The output of the comparator is latched on until a reset signal is received. The reset signal is produced when the ramp signal is discharged below a predetermined level. The programmable delay circuit is useful in a secondary side post regulator to control a totem pole driver. The totem pole driver in turn controls a switching device coupled to a voltage on a secondary winding.
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Citations
27 Claims
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1. An integrated circuit comprising:
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an error amplifier, connected to receive a voltage sense signal and a reference signal, so as to produce an error control signal; a ramp node for providing a periodic ramp signal; a reset signal generator arranged so as to produce a reset signal; a comparator connected to receive the error control signal and the ramp signal for generating a first state signal or a second state signal depending upon a comparison between the error control signal and the ramp signal; a latch circuit coupled to said reset signal generator and to said comparator in order to latch the first state signal until the reset signal is received; and an output driver, connected to a first terminal and a second terminal, switched in response to the first and second state signals to drive an output signal on the first terminal in response to the first state signal and to provide a low impedance path between the first terminal and the second terminal in response to the second state signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A switch with programmable delay comprising:
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an error amplifier, connected to receive a voltage sense signal and a reference signal, for producing an error output signal; buffer circuitry connected to receive the error output signal and produce an error control signal; a current source and a discharge transistor for producing a periodic ramp signal; a comparator connected to receive the error control signal and the ramp signal for generating a first state signal or a second state signal depending upon a comparison between the error control signal and the ramp signal; a latch circuit connected to said comparator in order to latch the first state signal until a reset signal is received; a current sense amplifier, connected to receive a current sense signal and a current limit reference signal and having an output coupled to said error amplifier, for causing, when an overcurrent condition is detected, said buffer circuitry to produce the error control signal relative to the ramp signal that causes said comparator to generate the second state signal; and an output driver, connected to a first terminal and a second terminal, switched in response to the first and second state signals to drive an output signal on the first terminal in response to the first state signal and to provide a low impedance path between the first terminal and the second terminal in response to the second state signal. - View Dependent Claims (8, 9, 10, 11)
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12. A switch with programmable delay comprising:
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Vcc means for receiving a supply voltage; a regulator connected to said supply voltage for generating a regulated voltage; an error amplifier, connected to receive a voltage sense signal and a reference signal, for producing an error control signal; a current source and a discharge transistor for producing a periodic ramp signal; a comparator connected to receive a voltage from the error control signal and the ramp signal for generating a first state signal or a second state signal depending upon a comparison between the voltage from the error control signal and the ramp signal; VregOK means for disabling said comparator when the regulated voltage is below a predetermined threshold; a latch circuit connected to said comparator in order to latch the first state signal until a reset signal is received; and an output driver, connected to a first terminal and a second terminal, switched in response to the first and second state signals to drive an output signal on the first terminal in response to the first state signal and to provide a low impedance path between the first terminal and the second terminal in response to the second state signal. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A secondary side post regulator comprising:
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a conductive line for receiving a sync signal corresponding to a voltage on a secondary winding; a programmable delay circuit, connected to receive a sense signal corresponding to a voltage at an output of a switching device, for generating a first state signal upon completion of a delay following a first edge of the sync signal, wherein the delay is determined by the sense signal, and for generating a second state signal in response to a second edge, opposite from the first edge, of the sync signal; a grounded totem pole driver, having a top output transistor and a bottom output transistor switched in response to the first and second state signals, to drive an output signal with the top output transistor on and the bottom output transistor off in response to the first state signal and to maintain a low impedance path through the bottom output transistor to ground with the top output transistor off in response to the second state signal until the first state signal is generated; and the switching device having the output, an input coupled to the voltage on the secondary winding and a control input coupled to the output signal of the grounded totem pole driver. - View Dependent Claims (19, 20, 21, 22)
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23. A secondary side post regulator comprising:
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a conductive line for receiving a sync signal corresponding to a voltage on a secondary winding; a programmable delay circuit, connected to receive a sense signal corresponding to a voltage at an output of a switching device, for generating a first state signal upon completion of a delay following an edge of the sync signal, wherein the delay is determined by the sense signal; a reset signal generator arranged so as to produce a reset signal; a latch circuit coupled to said reset signal generator and to said programmable delay circuit in order to latch the first state signal until the reset signal is received, wherein said programmable delay circuit generates a second state signal in response to the reset signal; a totem pole driver, having a top output transistor and a bottom output transistor switched in response to the first and second state signals, to drive an output signal with the top output transistor on and the bottom output transistor off in response to the first state signal and to maintain a low impedance path through the bottom output transistor with the top output transistor off in response to the second state signal; and the switching device having the output;
an input coupled to the voltage on the secondary winding and a control input coupled to the output signal of the totem pole driver. - View Dependent Claims (24, 25, 26, 27)
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Specification