Power amplifier and chip carrier

• US 5,955,926 A
• Filed: 10/02/1997
• Issued: 09/21/1999
• Est. Priority Date: 10/04/1996
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Uda, Hisanori, Okamoto, Shigeyuki
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Nguyen, Patricia T.
• Application Number:
  US08/942,980
• Time in Patent Office: 719 Days
• Field of Search: 330/286, 330/295, 330/302, 330/307, 330/277
• US Class Current: 330/295
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2924/19107 off-chip wires
• CPC Class Codes: H03F 3/604 using FET's

Abstract

A plurality of FETs have their respective gates connected to each other through a first line and their respective drains connected to each other through a second line. A gate bias is applied to the gate of each FET through the first line and a drain bias is applied to the drain of each FET through the second line. A first matching circuit includes first capacitors connected to the signal path, inductors each connected between one end of each first capacitor and the ground potential, and second capacitors each connected between the other end of each first capacitor and the ground potential. The second matching circuit includes first capacitors each connected to the signal path, second capacitors each connected between one end of each first capacitor and the ground potential, and inductors each connected between the other end of each first capacitor and the ground potential.

Claims

1. A power amplifier, comprising:

a plurality of transistors each having an input electrode, an output electrode, and a ground electrode;

a divider for distributing an input AC signal to the input electrodes of said plurality of transistors;

a first matching circuit for obtaining an impedance match between each of said plurality of transistors and said divider;

a combiner for combining AC signals outputted from the output electrodes of said plurality of transistors;

a second matching circuit for obtaining an impedance match between each of said plurality of transistors and said combiner;

a line provided separately from said combiner, for interconnecting the output electrodes of said plurality of transistors; and

a DC bias input portion receiving a DC bias, for applying said DC bias to the output electrodes of said plurality of transistors through said line without going through said combiner and said second matching circuit.

2. The power amplifier according to claim 1, wherein said second matching circuit comprises a plurality of capacitors each connected between the output electrode of each of said plurality of transistors and said combiner, and a plurality of inductors each connected between a connection between said combiner and each of said plurality of capacitors and a ground potential.

3. The power amplifier according to claim 1, wherein said second matching circuit comprises a plurality of first capacitors each connected between the output electrode of each of said plurality of transistors and said combiner, a plurality of second capacitors each connected between one end of each of said plurality of first capacitors and a ground potential, and a plurality of inductors each connected between the other end of each of said plurality of first capacitors and the ground potential.

4. The power amplifier according to claim 1, wherein said DC bias input portion is connected to a middle point of said line between the output electrodes of each adjacent two of the transistors.

5. The power amplifier according to claim 1, wherein

said input electrode is a gate electrode or a base electrode,

said output electrode is a drain electrode or a collector electrode, and

said ground electrode is a source electrode or an emitter electrode.

6. The power amplifier according to claim 1, wherein said plurality of transistors are mounted on a chip carrier.

7. The power amplifier according to claim 1, wherein said plurality of transistors are individually accommodated in packages.

8. A power amplifier, comprising:

a plurality of transistors each having an input electrode, an output electrode, and a ground electrode;

a divider for distributing an input AC signal to the input electrodes of said plurality of transistors;

a first matching circuit for obtaining an impedance match between each of said plurality of transistors and said divider;

a combiner for combining AC signals outputted from the output electrodes of said plurality of transistors;

a second matching circuit for obtaining an impedance match between each of said plurality of transistors and said combiner;

a line provided separately from said divider, for interconnecting the input electrodes of said plurality of transistors; and

a DC bias input portion receiving a DC bias, for applying said DC bias to the input electrodes of said plurality of transistors through said line without going through said divider and said first matching circuit.

9. The power amplifier according to claim 8, wherein said first matching circuit comprises a plurality of capacitors each connected between said divider and the input electrode of each of said plurality of transistors, and a plurality of inductors each connected between a connection between said divider and each of said plurality of capacitors and a ground potential.

10. The power amplifier according to claim 8, wherein said first matching circuit comprises a plurality of first capacitors each connected between said divider and the input electrode of each of said plurality of transistors, a plurality of inductors each connected between one end of each of said plurality of first capacitors and a ground potential, and a plurality of second capacitors each connected between the other end of each of said plurality of first capacitors and the ground potential.

11. The power amplifier according to claim 8, wherein said DC bias input portion is connected to a middle point of said line between the input electrodes of each adjacent two of the transistors.

12. The power amplifier according to claim 8, wherein

said input electrode is a gate electrode or a base electrode,

said output electrode is a drain electrode or a collector electrode, and

said ground electrode is a source electrode or an emitter electrode.

13. The power amplifier according to claim 8, wherein said plurality of transistors are mounted on a chip carrier.

14. The power amplifier according to claim 8, wherein said plurality of transistors are individually accommodated in packages.

15. A power amplifier, comprising:

a plurality of transistors each having an input electrode, an output electrode, and a ground electrode;

a divider for distributing an input AC signal to the input electrodes of said plurality of transistors;

a first matching circuit for obtaining an impedance match between each of said plurality of transistors and said divider;

a combiner for combining AC signals outputted from the output electrodes of said plurality of transistors;

a second matching circuit for obtaining an impedance match between each of said plurality of transistors and said combiner;

a first line provided separately from said divider, for interconnecting the input electrodes of said plurality of transistors;

a second line provided separately from said combiner, for interconnecting the output electrodes of said plurality of transistors;

a first DC bias input portion receiving a first DC bias, for applying said first DC bias to the input electrodes of said plurality of transistors through said first line without through said divider and said first matching circuit; and

a second DC bias input portion receiving a second DC bias, for applying said second DC bias to the output electrodes of said plurality of transistors through said second line without going through said combiner and said second matching circuit.

16. The power amplifier according to claim 15, wherein said second matching circuit comprises a plurality of capacitors each connected between the output electrode of each of said plurality of transistors and said combiner, and a plurality of inductors each connected between a connection between said combiner and each of said plurality of capacitors and a ground potential.

17. The power amplifier according to claim 15, wherein said second matching circuit comprises a plurality of first capacitors each connected between the output electrode of each of said plurality of transistors and said combiner, a plurality of second capacitors each connected between one end of each of said plurality of first capacitors and a ground potential, and a plurality of inductors each connected between the other end of each of said plurality of first capacitors and the ground potential.

18. The power amplifier according to claim 15, wherein said first matching circuit comprises a plurality of capacitors each connected between said divider and the input electrode of each of said plurality of transistors, and a plurality of inductors each connected between a connection between said divider and each of said plurality of capacitors and a ground potential.

19. The power amplifier according to claim 15, wherein said first matching circuit comprises a plurality of first capacitors each connected between said divider and the input electrode of each of said plurality of transistors, a plurality of inductors each connected between one end of each of said plurality of first capacitors and a ground potential, and a plurality of second capacitors each connected between the other end of each of said plurality of first capacitors and the ground potential.

20. The power amplifier according to claim 15,

wherein said first DC bias input portion is connected to a middle point of said first line between the input electrodes of each adjacent two of the transistors, and

said second DC bias input portion is connected to a middle point of said second line between the output electrodes of each adjacent two of the transistors.

21. The power amplifier according to claim 15, wherein

said divider has 2n output nodes,

said combiner has 2n input nodes,

said first matching circuit includes 2n first matching elements each connected to each of the 2n output nodes of said divider,

said second matching circuit includes 2n second matching elements each connected to each of the 2n input nodes of said combiner,

said first line interconnects output-side nodes of said 2n first matching elements, and

said second line interconnects input-side nodes of said 2n second matching elements.

22. The power amplifier according to claim 21, wherein

said plurality of transistors includes 2n transistors corresponding to said 2n first matching elements and said 2n second matching elements,

said input electrode of each said transistor being connected to the output-side node of a corresponding one of said first matching elements,

said output electrode of each said transistor being connected to the input-side node of a corresponding one of said second matching elements.

23. The power amplifier according to claim 21,

wherein said plurality of transistors include n transistors,

said input electrode of each said transistor corresponds to each two of said first matching elements, and is connected to a middle point of said first line between the output-side nodes of the corresponding two of said first matching elements, and

said output electrode of each said transistor corresponds to each two of said second matching elements, and is connected to a middle point of said second line between the input-side nodes of the corresponding two of said second matching elements.

24. The power amplifier according to claim 21,

wherein each said first matching element comprises a capacitor connected between a corresponding one of the output nodes of said divider and said output-side node, and an inductor connected between a corresponding one of the output nodes of said divider and a ground potential, and

each said second matching element comprises a capacitor connected between said input-side node and a corresponding one of the input nodes of said combiner and an inductor connected between a corresponding one of the input nodes of said combiner and the ground potential.

25. The power amplifier according to claim 24,

wherein each said first matching element further comprises a capacitor connected between said output-side node and the ground potential, and

each said second matching element further comprises a capacitor connected between said input-side node and the ground potential.

26. The power amplifier according to claim 15,

wherein said input electrode is a gate electrode or a base electrode,

said output electrode is a drain electrode or a collector electrode, and

said ground electrode is a source electrode or an emitter electrode.

27. The power amplifier according to claim 15,

wherein said plurality of transistors are mounted on a chip carrier,

said chip carrier comprising,

a substrate,

a first line which is formed on said substrate and to which the input electrodes of said plurality of transistors rare connected in common,

a second line which is formed on said substrate and to which the output electrodes of said plurality of transistors are connected in common, and

a ground conductor which is formed on said substrate and to which the ground electrodes of said plurality of transistors are connected in common.

28. The power amplifier according to claim 15, wherein said plurality of transistors are individually accommodated in packages.