Scene synchronization of multiple computer displays
First Claim
Patent Images
1. A computer system, comprising:
- a plurality of processing units, wherein each of said plurality of processing units includes a corresponding output signal, and wherein each of said plurality of processing units is configured to assert said corresponding output signal while performing a corresponding one of a first plurality of processing tasks;
a plurality of latch circuits, wherein each of said plurality of latch circuits is coupled to receive one said corresponding output signal from a respective one of said plurality of processing units as a corresponding latch input signal, and wherein each of said plurality of latch circuits is configured to latch said corresponding latch input signal as a corresponding latch output signal for a first time period beginning at a first point in time;
an indicator circuit coupled to receive each said corresponding latch output signal from said plurality of latch circuits, wherein said indicator circuit is configured to generate an indicator output signal indicative of whether any of said plurality of processing units was performing said corresponding one of said first plurality of processing tasks at said first point in time;
and wherein each of said plurality of processing units is configured to sample said indicator output signal at a second point in time subsequent to said first point in time, and wherein each of said plurality of processing units is configured to initiate a corresponding one of a second plurality of processing tasks in response to said indicator output signal indicating that all of said plurality of processing units have completed said corresponding one of said first plurality of tasks by said first point in time.
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Abstract
A multi-display video system for ensuring the proper synchronization of scene switching. Before each display switches to pixel data corresponding to the next scene to be rendered, new pixel data is written into a currently unused bank of frame buffer memory within a corresponding graphics accelerator. When each graphics accelerator in the video system has completed writing the new pixel data to its respective frame buffer, the scene switch may take place. Each graphics accelerator is configured to display an image corresponding to the next scene in response to the indicator output signal indicating that the pixel data updates for all graphics accelerators are complete.
175 Citations
31 Claims
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1. A computer system, comprising:
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a plurality of processing units, wherein each of said plurality of processing units includes a corresponding output signal, and wherein each of said plurality of processing units is configured to assert said corresponding output signal while performing a corresponding one of a first plurality of processing tasks; a plurality of latch circuits, wherein each of said plurality of latch circuits is coupled to receive one said corresponding output signal from a respective one of said plurality of processing units as a corresponding latch input signal, and wherein each of said plurality of latch circuits is configured to latch said corresponding latch input signal as a corresponding latch output signal for a first time period beginning at a first point in time; an indicator circuit coupled to receive each said corresponding latch output signal from said plurality of latch circuits, wherein said indicator circuit is configured to generate an indicator output signal indicative of whether any of said plurality of processing units was performing said corresponding one of said first plurality of processing tasks at said first point in time; and wherein each of said plurality of processing units is configured to sample said indicator output signal at a second point in time subsequent to said first point in time, and wherein each of said plurality of processing units is configured to initiate a corresponding one of a second plurality of processing tasks in response to said indicator output signal indicating that all of said plurality of processing units have completed said corresponding one of said first plurality of tasks by said first point in time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A multi-display video system for performing synchronization of scene switching, comprising:
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a plurality of display devices, wherein each of said plurality of display devices is configured to render a particular view of a given scene corresponding to a video input signal; a plurality of graphics accelerators corresponding to said plurality of display devices, wherein each of said plurality of graphics accelerators is configured to generate a video output signal received by a corresponding display device as said video input signal, wherein each of said plurality of graphics accelerators includes; a frame buffer memory unit, wherein said frame buffer memory unit includes a first memory bank and a second memory bank for storing pixel data; a digital-to-analog conversion (DAC) unit coupled to said frame buffer memory unit, wherein said DAC unit is configured to select said pixel data from said first memory bank for performing digital-to-analog conversion which generates said video output signal for conveyance to said corresponding display device, and wherein said DAC unit includes an in-progress signal, and wherein said DAC unit is configured to assert said in-progress signal while said corresponding graphics accelerator is writing pixel data for a next display scene to said second memory bank; a latch circuit, wherein said latch circuit is coupled to receive said in-progress signal as a latch input signal, and wherein said latch circuit is configured to latch said latch input signal as a latch output signal for a first time period beginning at a first point in time; an indicator circuit coupled to each of said plurality of graphics accelerators, wherein said indicator circuit is coupled to receive each said latch output signal, and wherein said indicator circuit is configured to generate an indicator output signal indicative of whether any of said plurality of graphics accelerators was performing said writing said pixel data for said next display scene to said second memory bank at said first point in time; and wherein each of said plurality of graphics accelerators is configured to sample said indicator output signal at a second point in time subsequent to said first point in time, and wherein said plurality of graphics accelerators are configured to concurrently cause said pixel data for said next display scene to be conveyed from said second memory bank to said corresponding display device in response to said indicator output signal indicating that all of said plurality of graphics accelerators have completed said writing said pixel data for said next display scene to said second memory bank by said first point in time. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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Specification