ROM-based control units in a geometry accelerator for a computer graphics system

• US 5,956,047 A
• Filed: 04/30/1997
• Issued: 09/21/1999
• Est. Priority Date: 04/30/1997
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Rojas, Edmundo, Rossin, Theodore G., Krech, Alan S. Jr., Ashburn, Jon L, Tucker, S Paul, Rakel, Ted, McGrath, Michael S, Strunk, Glenn W
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/846,363
• Time in Patent Office: 874 Days
• Field of Search: 345/501, 345/502, 345/503, 345/515, 345/522
• US Class Current: 345/503
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed. A plurality of control unit logic elements correspond respectively with the control units and control instruction branching within their respective control unit by defining the next address field. A branch central intelligence mechanism controls branching between the control units by defining the next address field.

Claims

1. A system for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system, comprising:

a plurality of processing elements;

a plurality of control units implemented in a read-only memory (ROM) via microcode instructions, said microcode instructions of said control units configured to utilize said processing elements in order to modify image data;

a branch central intelligence mechanism configured to control branching between said control units; and

a plurality of control unit logic elements corresponding respectively with said control units, each of said control unit logic elements configured to control branching within each of said control units.

2. The system of claim 1, wherein said control units are selected from the group consisting of a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, and a fog mechanism.

3. The system of claim 1, wherein said processing elements are selected from the group consisting of an arithmetic logic unit, a multiplier, a divider, a compare mechanism, and a clamp mechanism.

4. The system of claim 1, further comprising a next address field associated with each of said microcode instructions that defines a location in said ROM of a next instruction to be executed, wherein said central intelligence mechanism is configured to control branching between said control units by defining said next address field, and wherein each of said control unit logic elements is configured to control branching within its corresponding unit by defining said next address field.

5. A computer employing the system of claim 1.

6. A system for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system, comprising:

a plurality of processing elements;

a plurality of control units implemented in a read-only memory (ROM) via microcode instructions, said microcode instructions of said control units configured to utilize said processing elements in order to modify image data;

a next address field associated with each of said microcode instructions that defines a location in said ROM of a next instruction to be executed;

a central intelligence mechanism configured to control branching between said control units by defining said next address field; and

a plurality of control unit logic elements corresponding respectively with said control units, each of said control unit logic elements configured to control branching within its corresponding control unit by defining said next address field.

7. The system of claim 6, wherein said control units are selected from the group consisting of a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, and a fog mechanism.

8. The system of claim 6, wherein said processing elements are selected from the group consisting of an arithmetic logic unit, a multiplier, a divider, a compare mechanism, and a clamp mechanism.

9. A computer employing the system of claim 6.

10. A method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system, comprising:

implementing a plurality of processor elements;

implementing a plurality of control units in a read-only memory (ROM) via microcode instructions;

executing a microcode instruction associated with one of said microcoded control units with one of said processor elements in order to modify image data;

associating a next address field with each of said microcode instructions that defines a location in said ROM of a next instruction to be executed;

defining said next address field for a currently executing instruction based upon signals received from a branch central intelligence mechanism and a plurality of control unit logic elements corresponding respectively with said plurality of control units;

controlling branching between said control units with said branch central intelligence mechanism; and

controlling branching within each of said control units with a corresponding control unit logic element.

11. The method of claim 10 further comprising the step of providing said control units from the group consisting of a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, and a fog mechanism.

12. The method of claim 10, further comprising the step of providing said processing elements from the group consisting of an arithmetic logic unit, a multiplier, a divider, a compare mechanism, and a clamp mechanism.

13. A computer that implements the steps of the method of claim 10.