Adaptive distance protection system

• US 5,956,220 A
• Filed: 02/05/1998
• Issued: 09/21/1999
• Est. Priority Date: 02/05/1998
• Status: Expired due to Fees

• Current Assignee: ABB Network Partner AB (ABB Limited)
• Original Assignee: ABB Network Partner AB (ABB Limited), ABB Power T&D Co Inc (ABB Limited)
• Inventors: Saha, Murari M., Hu, Yi, Novosel, Damir
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): JACKSON, STEPHEN W
• Application Number:
  US09/019,321
• Time in Patent Office: 593 Days
• Field of Search: 361/62, 361/63, 361/64, 361/65, 361/78, 361/80, 361/115
• US Class Current: 361/62
• CPC Class Codes: H02H 3/40 responsive to ratio of voltage and current
• CPC Class Codes: H02H 7/267 for parallel lines and wires

Abstract

An adaptive distance relaying system provides improved performance for parallel circuit distance protection. The system utilizes the parallel circuit'"'"'s current, when available, in conjunction with measurements of voltage and current on the protected line to compensate for the zero sequence current mutual coupling effect. The sequence current ratio (zero or negative sequence) is used to avoid incorrect compensation for relays on the healthy circuit. If the parallel circuit current is not available and the line operating status is, the best zero sequence current compensation factors are selected accordingly as a next level adaptation. If both the parallel circuit current and line operating status are unavailable, a fallback scheme that offers better results than classical distance protection schemes is employed.

Claims

1. An adaptive distance protection method for use with an underreaching relay in a power system comprising a protected circuit and a parallel circuit, wherein said protected and parallel circuits are connected in parallel between a first bus (G) and a second bus (H), and wherein said underreaching relay comprises current and voltage measuring devices for measuring currents and voltages on said protected circuit, comprising the steps of:

(A) determining whether a measurement of current in said parallel circuit is available and, if so;

(A1) calculating a blocking criterion (α

₀ or α

₂);

(A2) determining whether said blocking criterion (α

₀ or α

₂) is less than a predefined default value;

(A3) if said blocking criterion is less than said default value, computing a compensated fault current using the zero sequence current (I_Psf0) in said parallel circuit;

(A4) if said blocking criterion is not less than said default value, computing the compensated fault current using a first zero sequence current compensation factor;

(B) if said current measurement is unavailable;

(B1) determining whether an operating status of said parallel circuit is available and, if so, whether said protected and parallel circuits are in operation;

(B2) if the parallel circuit'"'"'s operating status is available and both circuits are in operation, calculating a compensated fault current using a second zero sequence current compensation factor;

(B3) if the parallel circuit'"'"'s operating status is unavailable, calculating the compensated fault current using a third zero sequence compensation factor;

(B4) if the parallel circuit'"'"'s operating status is available and one line is not in operation, calculating the compensated fault current using a fourth zero sequence compensation factor; and

(C) calculating an apparent impedance value Z_apparent.

2. A method as recited in claim 1, wherein:

k₀ is determined by, k₀ =(Z_l0 -Z_l1) /Z_l1, where Z_l0 and Z_l1 are zero and positive sequence line impedances, respectively, in said protected circuit;

k₀ " is determined by,

k₀ "=Z_l0 *Z_AB0 -Z_l1 *Z_AB0 -Z²_0M /(Z_l1 *Z_AB0);

α

₀ is a ratio of zero sequence currents in the first and second circuits; and

α

₂ is a ratio of negative sequence currents in the first and second circuits;

wherein Z_0M is a zero sequence mutual coupling between the protected circuit and the parallel circuit; and

Z_AB0 is a zero sequence line impedance for the parallel circuit.

3. A method as recited in claim 2, wherein α

₀ and α

₂ are determined by;

α

₀ =|I_Psf0 /I_sf0 |

α

₁,2 =|I_Psf1,2 /I_sf1,2 |;

wherein I_sf0 is a zero sequence current at bus G;

I_sf1 is a positive sequence current at bus G;

I_sf2 is negative sequence current at but G;

I_Psf0 is a parallel circuit zero sequence current at bus G;

I_Psf1 is a parallel circuit positive sequence current at bus G; and

I_Psf2 is a parallel circuit negative sequence current at bus G.

4. A method as recited in claim 3, wherein Z_apparent is determined by Z_apparent =V_Gf /I^c_sfa, wherein I^c_sfa is compensated post-fault phase current and V_Gf is a measured post-fault voltage at bus G.

5. A method as recited in claim 4, wherein said first, second, third and fourth compensation factors are different from one another.

6. A method as recited in claim 4, wherein at least two of said first, second, third and fourth compensation factors are the same as one another.

7. An adaptive distance protection method for use with an overreaching relay in a power system comprising a protected circuit and a parallel circuit, wherein said protected and parallel circuits are connected in parallel between a first bus (G) and a second bus (H), and wherein said overreaching relay comprises current and voltage measuring devices for measuring currents and voltages on said protected circuit, comprising the steps of:

(A) determining whether a measurement of current in said parallel circuit is available and, if so;

(A1) calculating a blocking criterion (α

₀ or α

₂);

(A2) determining whether said blocking criterion (α

₀ or α

₂) is less than a predefined default value;

(A3) if said blocking criterion is less than said predefined default value, computing a compensated fault current using the zero sequence current (I_Psf0) in said parallel circuit;

(A4) if said blocking criterion is not less than said predefined default value, calculating a compensated fault current using a first zero sequence current compensation factor;

(B) if said current measurement is unavailable;

(B1) determining whether an operating status of said parallel circuit is available and, if so, whether the protected and parallel circuits are in operation;

(B2) if the parallel circuit'"'"'s operating status is available and both circuits are in operation, calculating a compensated fault current using a second zero sequence current compensation factor;

(B3) if the parallel circuit'"'"'s operating status is unavailable, calculating the compensated fault current using a third zero sequence compensation factor;

(B4) if the parallel circuit'"'"'s operating status is available and at least one line is not in operation, calculating the compensated fault current using a fourth zero sequence compensation factor; and

(C) calculating an apparent impedance value Z_apparent.

8. A method as recited in claim 7, wherein:

k₀ is determined by, k₀ =(Z_l0 -Z_l1)/Z_l1, where Z_l0 and Z_l1 are zero and positive sequence line impedances, respectively, in said protected circuit;

k₀ '"'"' is determined by,

K₀ '"'"'=(Z_l0-Zl1 +Z_0M)/Z_l1 ;

α

₀ is a ratio of zero sequence currents in the first and second circuits; and

α

₂ is a ratio of negative sequence currents in the first and second circuits;

wherein Z_0M is a zero sequence mutual coupling between the protected circuit and the parallel circuit; and

Z_AB0 is a zero sequence line impedance for the parallel circuit.

9. A method as recited in claim 8, wherein α

₀ and α

₂ are determined by;

α

₀ =|I_Psf0 /I_sf0 |,

α

₁,2 =|I_Psf1,2 /I_sf1,2 |;

wherein I_sf0 is a zero sequence current at bus G;

I_sf1 is a positive sequence current at bus G;

I_sf2 is negative sequence current at but G;

I_Psf0 is a parallel circuit zero sequence current at bus G;

I_Psf1 is a parallel circuit positive sequence current at bus G; and

I_Psf2 is a parallel circuit negative sequence current at bus G.

10. A method as recited in claim 9, wherein Z_apparent is determined by Z_apparent =V_Gf /I^C_sfa, wherein I^C_sfa is a compensated post-fault phase current and V_Gf is a measured post-fault voltage at bus G.

11. A method as recited in claim 10, wherein said first, second, third and fourth compensation factors are different from one another.

12. A method as recited in claim 10, wherein at least two of said first, second, third and fourth compensation factors are the same as one another.