Automated optimization of hierarchical netlists
First Claim
1. A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierarchical level, the method comprising the steps, performed by a programmed data processor, of:
- (i) receiving data defining said hierarchical netlist and timing constraints therefor;
(ii) establishing abstract timing models for all of said subsidiary cells;
(iii) propagating timing constraints to at least one selected subsidiary cell of said subsidiary cells;
(iv) optimizing said selected subsidiary cell by means of a flat optimizer to produce an optimized version of said selected subsidiary cell, wherein said upper-level cell contains a multiplicity of instances of said selected subsidiary cell, said optimizing step including the steps ofpropagating said timing constraints to each of a multiplicity of different cells of said selected subsidiary cell,merging said timing constraints for said multiplicity of instances of said selected subsidiary cell, to provide a merged set of timing constraints for all of said instances of said selected subsidiary cell, andoptimizing, in accordance with said merged set of timing constraints a single instance of said selected subsidiary cell with said flat optimizer, to produce said optimized version of said selected subsidiary cell; and
(v) substituting said optimized version of said selected subsidiary cell for all instances of said selected subsidiary cell into said netlist.
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Abstract
A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierachical level includes receiving data defining said netlist and timing constraints for it, and establishing abstract timing models for all the subsidiary cells. Timing constraints are propagated to at least one selected subsidiary cell and this cell is optimized by means of a flat optimizer to produced an optimized version of the selected subsidiary cell. The optimized version of the selected cell is inserted into the netlist. The timing constraints denote arrival times for signals at inputs of a cell and required times for signals at outputs of a cell and each abstract timing model of a cell comprises timing parameters which enable a delay time between a specified input of a cell to a specified output of a cell to be computed.
89 Citations
11 Claims
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1. A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierarchical level, the method comprising the steps, performed by a programmed data processor, of:
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(i) receiving data defining said hierarchical netlist and timing constraints therefor; (ii) establishing abstract timing models for all of said subsidiary cells; (iii) propagating timing constraints to at least one selected subsidiary cell of said subsidiary cells; (iv) optimizing said selected subsidiary cell by means of a flat optimizer to produce an optimized version of said selected subsidiary cell, wherein said upper-level cell contains a multiplicity of instances of said selected subsidiary cell, said optimizing step including the steps of propagating said timing constraints to each of a multiplicity of different cells of said selected subsidiary cell, merging said timing constraints for said multiplicity of instances of said selected subsidiary cell, to provide a merged set of timing constraints for all of said instances of said selected subsidiary cell, and optimizing, in accordance with said merged set of timing constraints a single instance of said selected subsidiary cell with said flat optimizer, to produce said optimized version of said selected subsidiary cell; and (v) substituting said optimized version of said selected subsidiary cell for all instances of said selected subsidiary cell into said netlist. - View Dependent Claims (2, 3, 4, 5)
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6. A method of fabricating an application-specific integrated circuit from a user-selected, input specification of said circuit, comprising the steps of:
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(a) performing by an automatic programmed data processor which includes a cell library the following steps; (1) responding to said user-selected, input specification to synthesize and generate a netlist composed of cells from said cell library; (2) optimizing said netlist; and (3) generating semiconductor mask data from the optimized netlist; and (b) fabricating the integrated circuit under control of said mask data;
wherein said netlist is a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierarchical level, said upper-level cell being incapable of optimization by a flat optimizer, and wherein the optimizing step comprises;(i) receiving data defining said netlist and timing constraints therefor; (ii) establishing abstract timing models for all said subsidiary cells; (iii) propagating timing constraints to at least one selected subsidiary cell; (iv) optimizing said selected cell by means of a flat optimizer to produce an optimized version of said selected subsidiary cell, wherein said upper-level cell contains a multiplicity of instances of said selected subsidiary cell, said optimizing step including the steps of propagating said timing constraints to each of a multiplicity of different cells of said selected subsidiary cell, merging the timing constraints for the multiplicity of instances of said selected subsidiary cell, to provide a merged set of timing constraints for all of said instances of said selected subsidiary cell, and optimizing, in accordance with said merged set of timing constraints a single instance of said selected subsidiary cell with said flat optimizer, to produce said optimized version of said selected subsidiary cell; and (v) substituting said optimized version of said selected subsidiary cell for all instances of said selected subsidiary cell into said netlist. - View Dependent Claims (7, 8, 9, 10, 11)
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Specification